SPARC: Take advantage of new PCState syntax.
This commit is contained in:
Gabe Black
@@ -46,18 +46,14 @@ decode OP default Unknown::unknown()
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{
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// Branch Always
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0x8: bpa(19, annul_code={{
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SparcISA::PCState pc = PCS;
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pc.npc(pc.pc() + disp);
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pc.nnpc(pc.npc() + 4);
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PCS = pc;
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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}});
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// Branch Never
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0x0: bpn(19, {{;}},
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annul_code={{
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.npc() + 8);
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pc.npc(pc.npc() + 4);
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PCS = pc;
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NNPC = NPC + 8;
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NPC = NPC + 4;
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}});
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default: decode BPCC
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{
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@@ -70,18 +66,14 @@ decode OP default Unknown::unknown()
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{
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// Branch Always
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0x8: ba(22, annul_code={{
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SparcISA::PCState pc = PCS;
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pc.npc(pc.pc() + disp);
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pc.nnpc(pc.npc() + 4);
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PCS = pc;
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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}});
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// Branch Never
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0x0: bn(22, {{;}},
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annul_code={{
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.npc() + 8);
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pc.npc(pc.npc() + 4);
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PCS = pc;
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NNPC = NPC + 8;
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NPC = NPC + 4;
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}});
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default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
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}
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@@ -105,18 +97,14 @@ decode OP default Unknown::unknown()
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format BranchN {
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// Branch Always
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0x8: fbpa(22, annul_code={{
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SparcISA::PCState pc = PCS;
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pc.npc(pc.pc() + disp);
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pc.nnpc(pc.npc() + 4);
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PCS = pc;
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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}});
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// Branch Never
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0x0: fbpn(22, {{;}},
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annul_code={{
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.npc() + 8);
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pc.npc(pc.npc() + 4);
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PCS = pc;
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NNPC = NPC + 8;
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NPC = NPC + 4;
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}});
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default: decode BPCC {
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0x0: fbpfcc0(19, test=
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@@ -135,18 +123,14 @@ decode OP default Unknown::unknown()
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format BranchN {
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// Branch Always
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0x8: fba(22, annul_code={{
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SparcISA::PCState pc = PCS;
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pc.npc(pc.pc() + disp);
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pc.nnpc(pc.npc() + 4);
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PCS = pc;
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NPC = PC + disp;
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NNPC = PC + disp + 4;
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}});
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// Branch Never
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0x0: fbn(22, {{;}},
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annul_code={{
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.npc() + 8);
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pc.npc(pc.npc() + 4);
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PCS = pc;
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NNPC = NPC + 8;
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NPC = NPC + 4;
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}});
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default: fbfcc(22, test=
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{{passesFpCondition(Fsr<11:10>, COND2)}});
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@@ -154,13 +138,11 @@ decode OP default Unknown::unknown()
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}
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}
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0x1: BranchN::call(30, {{
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SparcISA::PCState pc = PCS;
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if (Pstate<3:>)
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R15 = (pc.pc())<31:0>;
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R15 = (PC)<31:0>;
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else
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R15 = pc.pc();
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pc.nnpc(R15 + disp);
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PCS = pc;
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R15 = PC;
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NNPC = R15 + disp;
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}});
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0x2: decode OP3 {
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format IntOp {
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@@ -347,11 +329,10 @@ decode OP default Unknown::unknown()
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0x03: NoPriv::rdasi({{Rd = Asi;}});
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0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
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0x05: NoPriv::rdpc({{
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SparcISA::PCState pc = PCS;
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if (Pstate<3:>)
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Rd = (pc.pc())<31:0>;
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Rd = (PC)<31:0>;
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else
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Rd = pc.pc();
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Rd = PC;
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}});
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0x06: NoPriv::rdfprs({{
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// Wait for all fpops to finish.
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@@ -999,17 +980,18 @@ decode OP default Unknown::unknown()
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#if FULL_SYSTEM
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format BasicOperate {
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// we have 7 bits of space here to play with...
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0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
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}}, No_OpClass, IsNonSpeculative);
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0x21: m5exit({{
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PseudoInst::m5exit(xc->tcBase(), O0);
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}}, No_OpClass, IsNonSpeculative);
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0x50: m5readfile({{
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O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
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}}, IsNonSpeculative);
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0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
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}}, IsNonSpeculative);
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O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
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}}, IsNonSpeculative);
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0x51: m5break({{
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PseudoInst::debugbreak(xc->tcBase());
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}}, IsNonSpeculative);
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0x54: m5panic({{
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SparcISA::PCState pc = PCS;
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panic("M5 panic instruction called at pc=%#x.", pc.pc());
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}}, No_OpClass, IsNonSpeculative);
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panic("M5 panic instruction called at pc = %#x.", PC);
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}}, No_OpClass, IsNonSpeculative);
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}
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#endif
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default: Trap::impdep2({{fault = new IllegalInstruction;}});
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@@ -1019,13 +1001,11 @@ decode OP default Unknown::unknown()
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if (target & 0x3) {
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fault = new MemAddressNotAligned;
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} else {
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SparcISA::PCState pc = PCS;
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if (Pstate<3:>)
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Rd = (pc.pc())<31:0>;
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Rd = (PC)<31:0>;
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else
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Rd = pc.pc();
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pc.nnpc(target);
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PCS = pc;
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Rd = PC;
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NNPC = target;
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}
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}});
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0x39: Branch::return({{
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@@ -1041,9 +1021,7 @@ decode OP default Unknown::unknown()
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} else if (target & 0x3) { // Check for alignment faults
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fault = new MemAddressNotAligned;
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} else {
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SparcISA::PCState pc = PCS;
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pc.nnpc(target);
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PCS = pc;
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NNPC = target;
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Cwp = (Cwp - 1 + NWindows) % NWindows;
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Cansave = Cansave + 1;
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Canrestore = Canrestore - 1;
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@@ -1105,10 +1083,8 @@ decode OP default Unknown::unknown()
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Ccr = Tstate<39:32>;
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Gl = Tstate<42:40>;
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Hpstate = Htstate;
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SparcISA::PCState pc = PCS;
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pc.npc(Tnpc);
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pc.nnpc(Tnpc + 4);
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PCS = pc;
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NPC = Tnpc;
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NNPC = Tnpc + 4;
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Tl = Tl - 1;
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}}, checkTl=true);
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0x1: Priv::retry({{
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@@ -1118,10 +1094,8 @@ decode OP default Unknown::unknown()
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Ccr = Tstate<39:32>;
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Gl = Tstate<42:40>;
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Hpstate = Htstate;
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SparcISA::PCState pc = PCS;
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pc.npc(Tpc);
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pc.nnpc(Tnpc);
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PCS = pc;
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NPC = Tpc;
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NNPC = Tnpc;
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Tl = Tl - 1;
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}}, checkTl=true);
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}
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@@ -195,7 +195,6 @@ def template JumpExecute {{
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%(op_decl)s;
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%(op_rd)s;
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PCS = PCS;
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%(code)s;
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if (fault == NoFault) {
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@@ -242,6 +241,7 @@ def template BranchDecode {{
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// Primary format for branch instructions:
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def format Branch(code, *opt_flags) {{
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code = 'NNPC = NNPC;\n' + code
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(usesImm, code, immCode,
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rString, iString) = splitOutImm(code)
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iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
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@@ -290,24 +290,15 @@ let {{
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def doCondBranch(name, Name, base, cond, code, opt_flags):
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return doBranch(name, Name, base, cond, code, code,
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'PCS = PCS;',
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'''
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.npc() + 8);
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pc.npc(pc.npc() + 4);
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PCS = pc;
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''',
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'NNPC = NNPC; NPC = NPC;\n',
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'NNPC = NPC + 8; NPC = NPC + 4;\n',
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opt_flags)
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def doUncondBranch(name, Name, base, code, annul_code, opt_flags):
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return doBranch(name, Name, base, "true", code, annul_code,
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";", ";", opt_flags)
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default_branch_code = '''
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SparcISA::PCState pc = PCS;
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pc.nnpc(pc.pc() + disp);
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PCS = pc;
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'''
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default_branch_code = 'NNPC = PC + disp;\n'
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}};
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// Format for branch instructions with n bit displacements:
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@@ -129,7 +129,9 @@ def operands {{
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#'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
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'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
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'PCS': ('PCState', 'udw', None, (None, None, 'IsControl'), 30),
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'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
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'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
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'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
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# Registers which are used explicitly in instructions
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R1': ('IntReg', 'udw', '1', None, 7),
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