derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

configs: Fix apu_se.py CPU type checks (#651)

Browse Source 
The current checks do not work. Correct the CPU type names

Change-Id: I81778873df0567c4a8dabbbe659c4c7a39326f98
This commit is contained in:
Matthew Poremba
2023-12-04 19:14:46 -08:00
committed by GitHub
parent 569e21f798
commit f00d7f70a4
2 changed files with 13 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
configs/example/apu_se.py
View File

@@ -398,8 +398,8 @@ if buildEnv["PROTOCOL"] == "None":
fatal("GPU model requires ruby") fatal("GPU model requires ruby")
# Currently the gpu model requires only timing or detailed CPU # Currently the gpu model requires only timing or detailed CPU
if not (args.cpu_type == "TimingSimpleCPU" or args.cpu_type == "DerivO3CPU"): if not (args.cpu_type == "X86TimingSimpleCPU" or args.cpu_type == "X86O3CPU"):
fatal("GPU model requires TimingSimpleCPU or DerivO3CPU") fatal("GPU model requires X86TimingSimpleCPU or X86O3CPU.")
# This file can support multiple compute units # This file can support multiple compute units
assert args.num_compute_units >= 1 assert args.num_compute_units >= 1
@@ -571,7 +571,7 @@ cp_list = []
cpu_list = [] cpu_list = []
CpuClass, mem_mode = Simulation.getCPUClass(args.cpu_type) CpuClass, mem_mode = Simulation.getCPUClass(args.cpu_type)
if CpuClass == AtomicSimpleCPU: if CpuClass == X86AtomicSimpleCPU or CpuClass == AtomicSimpleCPU:
fatal("AtomicSimpleCPU is not supported") fatal("AtomicSimpleCPU is not supported")
if mem_mode != "timing": if mem_mode != "timing":
fatal("Only the timing memory mode is supported") fatal("Only the timing memory mode is supported")
@@ -825,18 +825,15 @@ for i in range(args.num_cpus):
system.cpu[i].dcache_port = ruby_port.in_ports system.cpu[i].dcache_port = ruby_port.in_ports
ruby_port.mem_request_port = system.piobus.cpu_side_ports ruby_port.mem_request_port = system.piobus.cpu_side_ports
if get_supported_isas().contains(ISA.X86):
system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports # X86 ISA is implied from cpu type check above
system.cpu[i].interrupts[ system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
0 system.cpu[i].interrupts[0].int_requestor = system.piobus.cpu_side_ports
].int_requestor = system.piobus.cpu_side_ports system.cpu[i].interrupts[0].int_responder = system.piobus.mem_side_ports
system.cpu[i].interrupts[ if fast_forward:
0 system.cpu[i].mmu.connectWalkerPorts(
].int_responder = system.piobus.mem_side_ports ruby_port.in_ports, ruby_port.in_ports
if fast_forward: )
system.cpu[i].mmu.connectWalkerPorts(
ruby_port.in_ports, ruby_port.in_ports
)
# attach CU ports to Ruby # attach CU ports to Ruby
# Because of the peculiarities of the CP core, you may have 1 CPU but 2 # Because of the peculiarities of the CP core, you may have 1 CPU but 2

2
configs/ruby/GPU_VIPER.py
View File

@@ -129,7 +129,7 @@ class CPCntrl(CorePair_Controller, CntrlBase):
self.sequencer1.is_cpu_sequencer = True self.sequencer1.is_cpu_sequencer = True
self.issue_latency = options.cpu_to_dir_latency self.issue_latency = options.cpu_to_dir_latency
self.send_evictions = send_evicts(options) self.send_evictions = True if options.cpu_type == "X86O3CPU" else False
self.ruby_system = ruby_system self.ruby_system = ruby_system