diff --git a/configs/example/apu_se.py b/configs/example/apu_se.py
index b375bbef7b..f9daf8a88b 100644
--- a/configs/example/apu_se.py
+++ b/configs/example/apu_se.py
@@ -398,8 +398,8 @@ if buildEnv["PROTOCOL"] == "None":
     fatal("GPU model requires ruby")
 
 # Currently the gpu model requires only timing or detailed CPU
-if not (args.cpu_type == "TimingSimpleCPU" or args.cpu_type == "DerivO3CPU"):
-    fatal("GPU model requires TimingSimpleCPU or DerivO3CPU")
+if not (args.cpu_type == "X86TimingSimpleCPU" or args.cpu_type == "X86O3CPU"):
+    fatal("GPU model requires X86TimingSimpleCPU or X86O3CPU.")
 
 # This file can support multiple compute units
 assert args.num_compute_units >= 1
@@ -571,7 +571,7 @@ cp_list = []
 cpu_list = []
 
 CpuClass, mem_mode = Simulation.getCPUClass(args.cpu_type)
-if CpuClass == AtomicSimpleCPU:
+if CpuClass == X86AtomicSimpleCPU or CpuClass == AtomicSimpleCPU:
     fatal("AtomicSimpleCPU is not supported")
 if mem_mode != "timing":
     fatal("Only the timing memory mode is supported")
@@ -825,18 +825,15 @@ for i in range(args.num_cpus):
     system.cpu[i].dcache_port = ruby_port.in_ports
 
     ruby_port.mem_request_port = system.piobus.cpu_side_ports
-    if get_supported_isas().contains(ISA.X86):
-        system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
-        system.cpu[i].interrupts[
-            0
-        ].int_requestor = system.piobus.cpu_side_ports
-        system.cpu[i].interrupts[
-            0
-        ].int_responder = system.piobus.mem_side_ports
-        if fast_forward:
-            system.cpu[i].mmu.connectWalkerPorts(
-                ruby_port.in_ports, ruby_port.in_ports
-            )
+
+    # X86 ISA is implied from cpu type check above
+    system.cpu[i].interrupts[0].pio = system.piobus.mem_side_ports
+    system.cpu[i].interrupts[0].int_requestor = system.piobus.cpu_side_ports
+    system.cpu[i].interrupts[0].int_responder = system.piobus.mem_side_ports
+    if fast_forward:
+        system.cpu[i].mmu.connectWalkerPorts(
+            ruby_port.in_ports, ruby_port.in_ports
+        )
 
 # attach CU ports to Ruby
 # Because of the peculiarities of the CP core, you may have 1 CPU but 2
diff --git a/configs/ruby/GPU_VIPER.py b/configs/ruby/GPU_VIPER.py
index 96d86f38d3..0818b7f0eb 100644
--- a/configs/ruby/GPU_VIPER.py
+++ b/configs/ruby/GPU_VIPER.py
@@ -129,7 +129,7 @@ class CPCntrl(CorePair_Controller, CntrlBase):
         self.sequencer1.is_cpu_sequencer = True
 
         self.issue_latency = options.cpu_to_dir_latency
-        self.send_evictions = send_evicts(options)
+        self.send_evictions = True if options.cpu_type == "X86O3CPU" else False
 
         self.ruby_system = ruby_system