python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/mem/AbstractMemory.py

@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class AbstractMemory(MemObject):
     type = 'AbstractMemory'

src/mem/AddrMapper.py

@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # An address mapper changes the packet addresses in going from the
 # slave port side of the mapper to the master port side. When the

src/mem/Bridge.py

@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'

src/mem/CommMonitor.py

@@ -38,8 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.MemObject import MemObject
+from m5.objects.System import System
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent

src/mem/DRAMCtrl.py

@@ -46,8 +46,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served

src/mem/ExternalMaster.py

@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalMaster(MemObject):
     type = 'ExternalMaster'

src/mem/ExternalSlave.py

@@ -36,7 +36,7 @@
 # Authors: Andrew Bardsley
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalSlave(MemObject):
     type = 'ExternalSlave'

src/mem/HMCController.py

@@ -39,7 +39,7 @@
 # Authors: Erfan Azarkhish
 
 from m5.params import *
-from XBar import *
+from m5.objects.XBar import *
 
 # References:
 # [1] http://www.open-silicon.com/open-silicon-ips/hmc/

src/mem/MemChecker.py

@@ -35,7 +35,7 @@
 #
 # Authors: Marco Elver
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *

src/mem/MemDelay.py

@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class MemDelay(MemObject):
     type = 'MemDelay'

src/mem/MemObject.py

@@ -26,7 +26,7 @@
 #
 # Authors: Ron Dreslinski
 
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 class MemObject(ClockedObject):
     type = 'MemObject'

src/mem/SerialLink.py

@@ -42,7 +42,7 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # SerialLink is a simple variation of the Bridge class, with the ability to
 # account for the latency of packet serialization.

src/mem/SimpleMemory.py

@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'

src/mem/XBar.py

@@ -39,12 +39,13 @@
 # Authors: Nathan Binkert
 #          Andreas Hansson
 
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
+from m5.objects.MemObject import MemObject
+
 class BaseXBar(MemObject):
     type = 'BaseXBar'
     abstract = True

src/mem/cache/Cache.py

@@ -42,10 +42,11 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from ReplacementPolicies import *
-from Tags import *
+
+from m5.objects.MemObject import MemObject
+from m5.objects.Prefetcher import BasePrefetcher
+from m5.objects.ReplacementPolicies import *
+from m5.objects.Tags import *
 
 
 # Enum for cache clusivity, currently mostly inclusive or mostly

src/mem/cache/prefetch/Prefetcher.py

@@ -39,12 +39,13 @@
 # Authors: Ron Dreslinski
 #          Mitch Hayenga
 
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
 from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
-from ReplacementPolicies import *
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
+from m5.objects.ReplacementPolicies import *
 
 class HWPProbeEvent(object):
     def __init__(self, prefetcher, obj, *listOfNames):

src/mem/cache/tags/Tags.py

@@ -37,8 +37,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
 
 class BaseTags(ClockedObject):
     type = 'BaseTags'

src/mem/probes/MemFootprintProbe.py

@@ -38,7 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemFootprintProbe(BaseMemProbe):
     type = "MemFootprintProbe"

src/mem/probes/MemTraceProbe.py

@@ -37,7 +37,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemTraceProbe(BaseMemProbe):
     type = 'MemTraceProbe'

src/mem/probes/StackDistProbe.py

@@ -38,7 +38,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class StackDistProbe(BaseMemProbe):
     type = 'StackDistProbe'

src/mem/qos/QoSMemCtrl.py

@@ -36,8 +36,8 @@
 # Authors: Matteo Andreozzi
 
 from m5.params import *
-from AbstractMemory import AbstractMemory
-from QoSTurnaround import *
+from m5.objects.AbstractMemory import AbstractMemory
+from m5.objects.QoSTurnaround import *
 
 # QoS Queue Selection policy used to select packets among same-QoS queues
 class QoSQPolicy(Enum): vals = ["fifo", "lifo", "lrg"]

src/mem/qos/QoSMemSinkCtrl.py

@@ -36,7 +36,7 @@
 # Author: Matteo Andreozzi
 
 from m5.params import *
-from QoSMemCtrl import *
+from m5.objects.QoSMemCtrl import *
 
 class QoSMemSinkCtrl(QoSMemCtrl):
     type = 'QoSMemSinkCtrl'

src/mem/ruby/network/BasicRouter.py

@@ -28,7 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
+
+from m5.objects.ClockedObject import ClockedObject
 
 class BasicRouter(ClockedObject):
     type = 'BasicRouter'

src/mem/ruby/network/Network.py

@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicLink
 
 class RubyNetwork(ClockedObject):
     type = 'RubyNetwork'

src/mem/ruby/network/garnet2.0/GarnetLink.py

@@ -30,8 +30,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class NetworkLink(ClockedObject):
     type = 'NetworkLink'

src/mem/ruby/network/garnet2.0/GarnetNetwork.py

@@ -30,9 +30,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from ClockedObject import ClockedObject
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.ClockedObject import ClockedObject
 
 class GarnetNetwork(RubyNetwork):
     type = 'GarnetNetwork'

src/mem/ruby/network/simple/SimpleLink.py

@@ -30,7 +30,7 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class SimpleExtLink(BasicExtLink):
     type = 'SimpleExtLink'

src/mem/ruby/network/simple/SimpleNetwork.py

@@ -29,9 +29,10 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from MessageBuffer import MessageBuffer
+
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.MessageBuffer import MessageBuffer
 
 class SimpleNetwork(RubyNetwork):
     type = 'SimpleNetwork'

src/mem/ruby/slicc_interface/Controller.py

@@ -41,7 +41,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyController(MemObject):
     type = 'RubyController'

src/mem/ruby/structures/LRUReplacementPolicy.py

@@ -31,7 +31,7 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class LRUReplacementPolicy(ReplacementPolicy):
     type = 'LRUReplacementPolicy'

src/mem/ruby/structures/PseudoLRUReplacementPolicy.py

@@ -27,7 +27,7 @@
 #
 # Author: Derek Hower
 
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class PseudoLRUReplacementPolicy(ReplacementPolicy):
     type = 'PseudoLRUReplacementPolicy'

src/mem/ruby/structures/RubyCache.py

@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
+from m5.objects.PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
 from m5.SimObject import SimObject
 
 class RubyCache(SimObject):

src/mem/ruby/structures/RubyPrefetcher.py

@@ -27,10 +27,11 @@
 # Authors: Nilay Vaish
 
 from m5.SimObject import SimObject
-from System import System
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.System import System
+
 class Prefetcher(SimObject):
     type = 'Prefetcher'
     cxx_class = 'Prefetcher'

src/mem/ruby/system/GPUCoalescer.py

@@ -34,7 +34,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Sequencer import *
+
+from m5.objects.Sequencer import *
 
 class RubyGPUCoalescer(RubyPort):
    type = 'RubyGPUCoalescer'

src/mem/ruby/system/RubySystem.py

@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from SimpleMemory import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.SimpleMemory import *
 
 class RubySystem(ClockedObject):
     type = 'RubySystem'

src/mem/ruby/system/Sequencer.py

@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyPort(MemObject):
    type = 'RubyPort'

src/mem/ruby/system/VIPERCoalescer.py

@@ -34,7 +34,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from GPUCoalescer import *
+from m5.objects.GPUCoalescer import *
 
 class VIPERCoalescer(RubyGPUCoalescer):
     type = 'VIPERCoalescer'

src/mem/ruby/system/WeightedLRUReplacementPolicy.py

@@ -33,8 +33,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.MemObject import MemObject
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class WeightedLRUReplacementPolicy(ReplacementPolicy):
     type = "WeightedLRUReplacementPolicy"

src/mem/slicc/symbols/StateMachine.py

@@ -226,7 +226,7 @@ class StateMachine(Symbol):
         code('''
 from m5.params import *
 from m5.SimObject import SimObject
-from Controller import RubyController
+from m5.objects.Controller import RubyController
 
 class $py_ident(RubyController):
     type = '$py_ident'