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python: Don't assume SimObjects live in the global namespace

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The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Andreas Sandberg
2019-01-25 14:26:21 +00:00
parent 9fbfb45e51
commit ef71a987c1
131 changed files with 300 additions and 267 deletions
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58
src/cpu/BaseCPU.py
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@@ -52,51 +52,51 @@ from m5.params import *
from m5.proxy import *
from m5.util.fdthelper import *
from XBar import L2XBar
from InstTracer import InstTracer
from CPUTracers import ExeTracer
from MemObject import MemObject
from SubSystem import SubSystem
from ClockDomain import *
from Platform import Platform
from m5.objects.XBar import L2XBar
from m5.objects.InstTracer import InstTracer
from m5.objects.CPUTracers import ExeTracer
from m5.objects.MemObject import MemObject
from m5.objects.SubSystem import SubSystem
from m5.objects.ClockDomain import *
from m5.objects.Platform import Platform
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
from AlphaInterrupts import AlphaInterrupts
from AlphaISA import AlphaISA
from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
from m5.objects.AlphaInterrupts import AlphaInterrupts
from m5.objects.AlphaISA import AlphaISA
default_isa_class = AlphaISA
elif buildEnv['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
from SparcInterrupts import SparcInterrupts
from SparcISA import SparcISA
from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
from m5.objects.SparcInterrupts import SparcInterrupts
from m5.objects.SparcISA import SparcISA
default_isa_class = SparcISA
elif buildEnv['TARGET_ISA'] == 'x86':
from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
from X86LocalApic import X86LocalApic
from X86ISA import X86ISA
from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
from m5.objects.X86LocalApic import X86LocalApic
from m5.objects.X86ISA import X86ISA
default_isa_class = X86ISA
elif buildEnv['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
from MipsInterrupts import MipsInterrupts
from MipsISA import MipsISA
from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
from m5.objects.MipsInterrupts import MipsInterrupts
from m5.objects.MipsISA import MipsISA
default_isa_class = MipsISA
elif buildEnv['TARGET_ISA'] == 'arm':
from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
from ArmInterrupts import ArmInterrupts
from ArmISA import ArmISA
from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
from m5.objects.ArmInterrupts import ArmInterrupts
from m5.objects.ArmISA import ArmISA
default_isa_class = ArmISA
elif buildEnv['TARGET_ISA'] == 'power':
from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
from PowerInterrupts import PowerInterrupts
from PowerISA import PowerISA
from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
from m5.objects.PowerInterrupts import PowerInterrupts
from m5.objects.PowerISA import PowerISA
default_isa_class = PowerISA
elif buildEnv['TARGET_ISA'] == 'riscv':
from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
from RiscvInterrupts import RiscvInterrupts
from RiscvISA import RiscvISA
from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
from m5.objects.RiscvInterrupts import RiscvInterrupts
from m5.objects.RiscvISA import RiscvISA
default_isa_class = RiscvISA
class BaseCPU(MemObject):