arch-arm: Convert to the new faulting logic

This patch is moving trapping behaviour modelled in
MiscRegOp64::trap to the MiscRegLUTEntry fault callbacks.

Change-Id: Idfca428e9e6669b747de0255888fc8a85a1f5d07
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61683
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.hh

@@ -204,6 +204,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
     static const AddrRange GICH_APR;
     static const AddrRange GICH_LR;
 
+  public:
     BitUnion64(ICH_HCR_EL2)
         Bitfield<63, 32> res0_2;
         Bitfield<31, 27> EOIcount;
@@ -224,6 +225,7 @@ class Gicv3CPUInterface : public ArmISA::BaseISADevice, public Serializable
         Bitfield<0>      En;
     EndBitUnion(ICH_HCR_EL2)
 
+  protected:
     BitUnion64(ICH_LR_EL2)
         Bitfield<63, 62> State;
         Bitfield<61>     HW;