arch-arm: Add generateTrap method to MiscRegOp64

Change-Id: I176cdb63284e146ce376344d895fdbf6c42b883d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61682
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/insts/misc64.cc

@@ -813,6 +813,28 @@ MiscRegOp64::_iss(const MiscRegNum64 &misc_reg, RegIndex int_index) const
         (misc_reg.op0 << 20);
 }
 
+Fault
+MiscRegOp64::generateTrap(ExceptionLevel el) const
+{
+    return generateTrap(el, EC_TRAPPED_MSR_MRS_64, iss());
+}
+
+Fault
+MiscRegOp64::generateTrap(ExceptionLevel el, ExceptionClass ec,
+        uint32_t iss) const
+{
+    switch (el) {
+      case EL1:
+        return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
+      case EL2:
+        return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
+      case EL3:
+        return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
+      default:
+        panic("Invalid EL: %d\n", el);
+    }
+}
+
 RegVal
 MiscRegImmOp64::miscRegImm() const
 {

src/arch/arm/insts/misc64.hh

@@ -155,6 +155,10 @@ class MiscRegOp64 : public ArmISA::ArmStaticInst
     virtual uint32_t iss() const { return 0; }
 
     bool miscRead() const { return _miscRead; }
+
+    Fault generateTrap(ArmISA::ExceptionLevel el) const;
+    Fault generateTrap(ArmISA::ExceptionLevel el,
+            ArmISA::ExceptionClass ec, uint32_t iss) const;
 };
 
 class MiscRegImmOp64 : public MiscRegOp64