arch-arm: Add DVM enabled flag in the Decoder class

This is needed as the decoder needs to choose whether to
instantiate a DVM (treated as IsLoad) instruction when
decoding a TLBI/DSB Shareable, or to issue a simple system
instruction in case DVM messages are not modelled in the
simulated system.

JIRA: https://gem5.atlassian.net/browse/GEM5-1097

Change-Id: I9f46304dee63851caec809a5c6b8e796d684cc05
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56603
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/decoder.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014,2018 ARM Limited
+ * Copyright (c) 2012-2014,2018, 2021 Arm Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -55,7 +55,9 @@ namespace ArmISA
 GenericISA::BasicDecodeCache<Decoder, ExtMachInst> Decoder::defaultCache;
 
 Decoder::Decoder(const ArmDecoderParams &params)
-    : InstDecoder(params, &data), data(0), fpscrLen(0), fpscrStride(0),
+    : InstDecoder(params, &data),
+      dvmEnabled(params.dvm_enabled),
+      data(0), fpscrLen(0), fpscrStride(0),
       decoderFlavor(dynamic_cast<ISA *>(params.isa)->decoderFlavor())
 {
     reset();