Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last
src/arch/sparc/isa/decoder.isa:
Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
Add IsFirstMicroop flag to static insts
--HG--
extra : convert_revision : 02bea93d38c03bbafe4570665eb4c01c11caa2fc
This commit is contained in:
@@ -1079,6 +1079,9 @@ decode OP default Unknown::unknown()
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//ASI_LDTX_N_L
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0x2F: TwinLoad::ldtx_n_l(
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{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
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//ASI_LDTX_P
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0xE2: TwinLoad::ldtx_p(
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{{RdTwin.udw = Mem.udw}}, {{EXT_ASI}});
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default: ldtwa({{
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uint64_t val = Mem.udw;
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RdLow = val<31:0>;
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@@ -1,4 +1,4 @@
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// Copyright (c) 2006 The Regents of The University of Michigan
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// Copyright (c) 2006-2007 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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@@ -451,6 +451,8 @@ let {{
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flag_code = ''
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if (microPc == 7):
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flag_code = "flags[IsLastMicroOp] = true;"
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elif (microPc == 0):
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flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
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else:
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flag_code = "flags[IsDelayedCommit] = true;"
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pcedCode = matcher.sub("Frd_%d" % microPc, code)
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@@ -492,7 +494,7 @@ let {{
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flag_code = "flags[IsLastMicroOp] = true;"
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pcedCode = matcher.sub("RdHigh", code)
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else:
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flag_code = "flags[IsDelayedCommit] = true;"
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flag_code = "flags[IsDelayedCommit] = true; flags[IsFirstMicroOp] = true;"
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pcedCode = matcher.sub("RdLow", code)
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iop = InstObjParams(name, Name, 'TwinMem', pcedCode,
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opt_flags, {"ea_code": addrCalcReg,
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