arch,cpu: Use PCStateBase in StaticInst::branchTarget

Change-Id: I1b8a2ea088b52252601968b1b1083ed712a5bfd6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52045
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

src/cpu/nop_static_inst.cc

@@ -29,6 +29,7 @@
 #include "cpu/nop_static_inst.hh"
 
 #include "arch/pcstate.hh"
+#include "config/the_isa.hh"
 #include "cpu/static_inst.hh"
 
 namespace gem5

src/cpu/o3/decode.cc

@@ -292,7 +292,7 @@ Decode::squash(const DynInstPtr &inst, ThreadID tid)
     toFetch->decodeInfo[tid].mispredictInst = inst;
     toFetch->decodeInfo[tid].squash = true;
     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
-    toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
+    set(toFetch->decodeInfo[tid].nextPC, *inst->branchTarget());
 
     // Looking at inst->pcState().branching()
     // may yield unexpected results if the branch
@@ -715,21 +715,21 @@ Decode::decodeInsts(ThreadID tid)
         {
             ++stats.branchResolved;
 
-            if (!(inst->branchTarget() == inst->readPredTarg())) {
+            if (*inst->branchTarget() != inst->readPredTarg()) {
                 ++stats.branchMispred;
 
                 // Might want to set some sort of boolean and just do
                 // a check at the end
                 squash(inst, inst->threadNumber);
-                TheISA::PCState target = inst->branchTarget();
+                std::unique_ptr<PCStateBase> target = inst->branchTarget();
 
                 DPRINTF(Decode,
                         "[tid:%i] [sn:%llu] "
                         "Updating predictions: Wrong predicted target: %s \
                         PredPC: %s\n",
-                        tid, inst->seqNum, inst->readPredTarg(), target);
+                        tid, inst->seqNum, inst->readPredTarg(), *target);
                 //The micro pc after an instruction level branch should be 0
-                inst->setPredTarg(target);
+                inst->setPredTarg(target->as<TheISA::PCState>());
                 break;
             }
         }

src/cpu/o3/dyn_inst.hh

@@ -717,7 +717,7 @@ class DynInst : public ExecContext, public RefCounted
     OpClass opClass() const { return staticInst->opClass(); }
 
     /** Returns the branch target address. */
-    TheISA::PCState
+    std::unique_ptr<PCStateBase>
     branchTarget() const
     {
         return staticInst->branchTarget(pc);

src/cpu/static_inst.cc

@@ -40,14 +40,14 @@ StaticInst::fetchMicroop(MicroPC upc) const
           "that is not microcoded.");
 }
 
-TheISA::PCState
-StaticInst::branchTarget(const TheISA::PCState &pc) const
+std::unique_ptr<PCStateBase>
+StaticInst::branchTarget(const PCStateBase &pc) const
 {
     panic("StaticInst::branchTarget() called on instruction "
           "that is not a PC-relative branch.");
 }
 
-TheISA::PCState
+std::unique_ptr<PCStateBase>
 StaticInst::branchTarget(ThreadContext *tc) const
 {
     panic("StaticInst::branchTarget() called on instruction "

src/cpu/static_inst.hh

@@ -47,10 +47,9 @@
 #include <memory>
 #include <string>
 
-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/logging.hh"
 #include "base/refcnt.hh"
-#include "config/the_isa.hh"
 #include "cpu/op_class.hh"
 #include "cpu/reg_class.hh"
 #include "cpu/static_inst_fwd.hh"
@@ -339,7 +338,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
      * should be true).
      */
-    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
+    virtual std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &pc) const;
 
     /**
      * Return the target address for an indirect branch (jump).  The
@@ -348,7 +348,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * execute the branch in question.  Invalid if not an indirect
      * branch (i.e. isIndirectCtrl() should be true).
      */
-    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
+    virtual std::unique_ptr<PCStateBase> branchTarget(
+            ThreadContext *tc) const;
 
     /**
      * Return string representation of disassembled instruction.