diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index b8a22fc197..4c9552df90 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -43,31 +43,34 @@ namespace gem5
 namespace ArmISA
 {
 
-ArmISA::PCState
-BranchImm64::branchTarget(const ArmISA::PCState &branchPC) const
+std::unique_ptr<PCStateBase>
+BranchImm64::branchTarget(const PCStateBase &branch_pc) const
 {
-    ArmISA::PCState pcs = branchPC;
-    pcs.instNPC(pcs.pc() + imm);
-    pcs.advance();
-    return pcs;
+    PCStateBase *pcs = branch_pc.clone();
+    auto &apc = pcs->as<PCState>();
+    apc.instNPC(apc.pc() + imm);
+    apc.advance();
+    return std::unique_ptr<PCStateBase>{pcs};
 }
 
-ArmISA::PCState
-BranchImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
+std::unique_ptr<PCStateBase>
+BranchImmReg64::branchTarget(const PCStateBase &branch_pc) const
 {
-    ArmISA::PCState pcs = branchPC;
-    pcs.instNPC(pcs.pc() + imm);
-    pcs.advance();
-    return pcs;
+    PCStateBase *pcs = branch_pc.clone();
+    auto &apc = pcs->as<PCState>();
+    apc.instNPC(apc.pc() + imm);
+    apc.advance();
+    return std::unique_ptr<PCStateBase>{pcs};
 }
 
-ArmISA::PCState
-BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
+std::unique_ptr<PCStateBase>
+BranchImmImmReg64::branchTarget(const PCStateBase &branch_pc) const
 {
-    ArmISA::PCState pcs = branchPC;
-    pcs.instNPC(pcs.pc() + imm2);
-    pcs.advance();
-    return pcs;
+    PCStateBase *pcs = branch_pc.clone();
+    auto &apc = pcs->as<PCState>();
+    apc.instNPC(apc.pc() + imm2);
+    apc.advance();
+    return std::unique_ptr<PCStateBase>{pcs};
 }
 
 std::string
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh
index 10483a6516..551ade7e3b 100644
--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -57,8 +57,8 @@ class BranchImm64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
     {}
 
-    ArmISA::PCState branchTarget(
-            const ArmISA::PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -180,8 +180,8 @@ class BranchImmReg64 : public ArmStaticInst
         ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
     {}
 
-    ArmISA::PCState branchTarget(
-            const ArmISA::PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -206,8 +206,8 @@ class BranchImmImmReg64 : public ArmStaticInst
         imm1(_imm1), imm2(_imm2), op1(_op1)
     {}
 
-    ArmISA::PCState branchTarget(
-            const ArmISA::PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index 91826a2dfd..fd48bad912 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -46,7 +46,7 @@ let {{
         bCode = '''
         NPC = (uint32_t)(PC + imm);
         '''
-        br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
+        br_tgt_code = '''pcs.instNPC((uint32_t)(pcs.instPC() + imm));'''
         instFlags = ["IsDirectControl"]
         if (link):
             bCode += '''
@@ -86,8 +86,8 @@ let {{
             # of the current ISA. Thumb is whether the target is ARM.
             newPC = '(uint32_t)(Thumb ? (roundDown(PC, 4) + imm) : (PC + imm))'
             br_tgt_code = '''
-            pcs.instNPC((uint32_t)(branchPC.thumb() ? (roundDown(branchPC.instPC(),4) + imm) :
-                                (branchPC.instPC() + imm)));
+            pcs.instNPC((uint32_t)(pcs.thumb() ? (roundDown(pcs.instPC(), 4) +
+                            imm) : (pcs.instPC() + imm)));
             '''
             base = "BranchImmCond"
             declare = BranchImmCondDeclare
@@ -129,8 +129,7 @@ let {{
                 NextThumb = !Thumb;
                 NPC = %(newPC)s;
             '''
-            br_tgt_code = '''pcs.nextThumb(!branchPC.thumb());\n''' + \
-                          br_tgt_code
+            br_tgt_code = '''pcs.nextThumb(!pcs.thumb());\n''' + br_tgt_code
         else:
             branchStr = "IWNPC = %(newPC)s;"
         branchStr = branchStr % { "newPC" : newPC }
@@ -171,7 +170,7 @@ let {{
     #CBNZ, CBZ. These are always unconditional as far as predicates
     for (mnem, test) in (("cbz", "=="), ("cbnz", "!=")):
         code = 'NPC = (uint32_t)(PC + imm);\n'
-        br_tgt_code = '''pcs.instNPC((uint32_t)(branchPC.instPC() + imm));'''
+        br_tgt_code = '''pcs.instNPC((uint32_t)(pcs.instPC() + imm));'''
         predTest = "Op1 %(test)s 0" % {"test": test}
         iop = ArmInstObjParams(mnem, mnem.capitalize(), "BranchImmReg",
                                { "code" : code, "predicate_test" : predTest,
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 3bb9e6b2b4..b42a00fbc3 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -46,8 +46,8 @@ class %(class_name)s : public %(base_class)s
     %(class_name)s(ExtMachInst machInst, int32_t _imm,
                    ConditionCode _condCode);
     Fault execute(ExecContext *, Trace::InstRecord *) const override;
-    ArmISA::PCState branchTarget(
-            const ArmISA::PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -150,8 +150,8 @@ class %(class_name)s : public %(base_class)s
     // Constructor
     %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1);
     Fault execute(ExecContext *, Trace::InstRecord *) const override;
-    ArmISA::PCState branchTarget(
-            const ArmISA::PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -173,16 +173,17 @@ def template BranchImmRegConstructor {{
 
 def template BranchTarget {{
 
-    ArmISA::PCState
-    %(class_name)s::branchTarget(const ArmISA::PCState &branchPC) const
+    std::unique_ptr<PCStateBase>
+    %(class_name)s::branchTarget(const PCStateBase &branch_pc) const
     {
         %(op_decl)s;
         %(op_rd)s;
 
-        ArmISA::PCState pcs = branchPC;
+        PCStateBase *pc_ptr = branch_pc.clone();
+        auto &pcs = pc_ptr->as<ArmISA::PCState>();
         %(brTgtCode)s
         pcs.advance();
-        return pcs;
+        return std::unique_ptr<PCStateBase>{pc_ptr};
     }
 }};
 
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 5cbc8a59c4..96841cfa4a 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -86,8 +86,8 @@ output header {{
             }
         }
 
-        MipsISA::PCState branchTarget(
-                const MipsISA::PCState &branchPC) const override;
+        std::unique_ptr<PCStateBase> branchTarget(
+                const PCStateBase &branch_pc) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
@@ -117,7 +117,8 @@ output header {{
         {
         }
 
-        MipsISA::PCState branchTarget(ThreadContext *tc) const override;
+        std::unique_ptr<PCStateBase> branchTarget(
+                ThreadContext *tc) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
@@ -128,25 +129,27 @@ output header {{
 }};
 
 output decoder {{
-    MipsISA::PCState
-    Branch::branchTarget(const MipsISA::PCState &branchPC) const
+    std::unique_ptr<PCStateBase>
+    Branch::branchTarget(const PCStateBase &branch_pc) const
     {
-        MipsISA::PCState target = branchPC;
+        PCStateBase *target_ptr = branch_pc.clone();
+        auto &target = target_ptr->as<MipsISA::PCState>();
         target.advance();
-        target.npc(branchPC.pc() + sizeof(MachInst) + disp);
+        target.npc(branch_pc.instAddr() + sizeof(MachInst) + disp);
         target.nnpc(target.npc() + sizeof(MachInst));
-        return target;
+        return std::unique_ptr<PCStateBase>{target_ptr};
     }
 
-    MipsISA::PCState
+    std::unique_ptr<PCStateBase>
     Jump::branchTarget(ThreadContext *tc) const
     {
-        MipsISA::PCState target = tc->pcState();
+        PCStateBase *target_ptr = tc->pcState().clone();
+        auto &target = target_ptr->as<MipsISA::PCState>();
         Addr pc = target.pc();
         target.advance();
         target.npc((pc & 0xF0000000) | disp);
         target.nnpc(target.npc() + sizeof(MachInst));
-        return target;
+        return std::unique_ptr<PCStateBase>{target_ptr};
     }
 
     const std::string &
diff --git a/src/arch/power/insts/branch.cc b/src/arch/power/insts/branch.cc
index 861bacd43a..2cab370acd 100644
--- a/src/arch/power/insts/branch.cc
+++ b/src/arch/power/insts/branch.cc
@@ -56,7 +56,7 @@ PCDependentDisassembly::disassemble(
 }
 
 
-PowerISA::PCState
+std::unique_ptr<PCStateBase>
 BranchOp::branchTarget(ThreadContext *tc) const
 {
     Msr msr = tc->readIntReg(INTREG_MSR);
@@ -67,7 +67,8 @@ BranchOp::branchTarget(ThreadContext *tc) const
     else
         addr = tc->pcState().pc() + li;
 
-    return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
+    return std::make_unique<PowerISA::PCState>(
+            msr.sf ? addr : addr & UINT32_MAX);
 }
 
 
@@ -104,7 +105,7 @@ BranchOp::generateDisassembly(
 }
 
 
-PowerISA::PCState
+std::unique_ptr<PCStateBase>
 BranchDispCondOp::branchTarget(ThreadContext *tc) const
 {
     Msr msr = tc->readIntReg(INTREG_MSR);
@@ -115,7 +116,8 @@ BranchDispCondOp::branchTarget(ThreadContext *tc) const
     else
         addr = tc->pcState().pc() + bd;
 
-    return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
+    return std::make_unique<PowerISA::PCState>(
+            msr.sf ? addr : addr & UINT32_MAX);
 }
 
 
@@ -155,12 +157,13 @@ BranchDispCondOp::generateDisassembly(
 }
 
 
-PowerISA::PCState
+std::unique_ptr<PCStateBase>
 BranchRegCondOp::branchTarget(ThreadContext *tc) const
 {
     Msr msr = tc->readIntReg(INTREG_MSR);
     Addr addr = tc->readIntReg(srcRegIdx(_numSrcRegs - 1).index()) & -4ULL;
-    return PowerISA::PCState(msr.sf ? addr : addr & UINT32_MAX);
+    return std::make_unique<PowerISA::PCState>(
+            msr.sf ? addr : addr & UINT32_MAX);
 }
 
 
diff --git a/src/arch/power/insts/branch.hh b/src/arch/power/insts/branch.hh
index 1359086b0b..d96bcfe1b1 100644
--- a/src/arch/power/insts/branch.hh
+++ b/src/arch/power/insts/branch.hh
@@ -88,7 +88,8 @@ class BranchOp : public PCDependentDisassembly
     {
     }
 
-    PowerISA::PCState branchTarget(ThreadContext *tc) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            ThreadContext *tc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -159,7 +160,8 @@ class BranchDispCondOp : public BranchCondOp
     {
     }
 
-    PowerISA::PCState branchTarget(ThreadContext *tc) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            ThreadContext *tc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
@@ -186,7 +188,8 @@ class BranchRegCondOp : public BranchCondOp
     {
     }
 
-    PowerISA::PCState branchTarget(ThreadContext *tc) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            ThreadContext *tc) const override;
 
     /// Explicitly import the otherwise hidden branchTarget
     using StaticInst::branchTarget;
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index ce58e54271..3c16f60e50 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -175,8 +175,8 @@ def template BranchDeclare {{
         generateDisassembly(
                 Addr pc, const loader::SymbolTable *symtab) const override;
 
-        RiscvISA::PCState
-        branchTarget(const RiscvISA::PCState &branchPC) const override;
+        std::unique_ptr<PCStateBase> branchTarget(
+                const PCStateBase &branch_pc) const override;
 
         using StaticInst::branchTarget;
     };
@@ -194,10 +194,11 @@ def template BranchExecute {{
         return NoFault;
     }
 
-    RiscvISA::PCState
-    %(class_name)s::branchTarget(const RiscvISA::PCState &branchPC) const
+    std::unique_ptr<PCStateBase>
+    %(class_name)s::branchTarget(const PCStateBase &branch_pc) const
     {
-        return RiscvISA::PCState(branchPC.pc() + imm);
+        auto &rpc = branch_pc.as<RiscvISA::PCState>();
+        return std::make_unique<PCState>(rpc.pc() + imm);
     }
 
     std::string
@@ -232,8 +233,8 @@ def template JumpDeclare {{
         generateDisassembly(
                 Addr pc, const loader::SymbolTable *symtab) const override;
 
-        RiscvISA::PCState
-        branchTarget(ThreadContext *tc) const override;
+        std::unique_ptr<PCStateBase> branchTarget(
+                ThreadContext *tc) const override;
 
         using StaticInst::branchTarget;
     };
@@ -251,12 +252,12 @@ def template JumpExecute {{
         return NoFault;
     }
 
-    RiscvISA::PCState
+    std::unique_ptr<PCStateBase>
     %(class_name)s::branchTarget(ThreadContext *tc) const
     {
         PCState pc = tc->pcState();
         pc.set((tc->readIntReg(srcRegIdx(0).index()) + imm)&~0x1);
-        return pc;
+        return std::unique_ptr<PCStateBase>{pc.clone()};
     }
 
     std::string
diff --git a/src/arch/x86/insts/microop.cc b/src/arch/x86/insts/microop.cc
index 12b5f948c5..4630a3b2ec 100644
--- a/src/arch/x86/insts/microop.cc
+++ b/src/arch/x86/insts/microop.cc
@@ -122,15 +122,16 @@ X86MicroopBase::checkCondition(uint64_t flags, int condition) const
     return true;
 }
 
-PCState
-X86MicroopBase::branchTarget(const PCState &branchPC) const
+std::unique_ptr<PCStateBase>
+X86MicroopBase::branchTarget(const PCStateBase &branch_pc) const
 {
-    PCState pcs = branchPC;
-        DPRINTF(X86, "branchTarget PC info: %s, Immediate: %lx\n", pcs,
-                (int64_t)machInst.immediate);
-    pcs.npc(pcs.npc() + (int64_t)machInst.immediate);
-    pcs.uEnd();
-    return pcs;
+    PCStateBase *pcs = branch_pc.clone();
+    DPRINTF(X86, "branchTarget PC info: %s, Immediate: %lx\n", *pcs,
+            (int64_t)machInst.immediate);
+    auto &xpc = pcs->as<PCState>();
+    xpc.npc(xpc.npc() + (int64_t)machInst.immediate);
+    xpc.uEnd();
+    return std::unique_ptr<PCStateBase>{pcs};
 }
 
 } // namespace X86ISA
diff --git a/src/arch/x86/insts/microop.hh b/src/arch/x86/insts/microop.hh
index 350294faa2..5fa0e37210 100644
--- a/src/arch/x86/insts/microop.hh
+++ b/src/arch/x86/insts/microop.hh
@@ -142,7 +142,8 @@ class X86MicroopBase : public X86StaticInst
             xpc.uAdvance();
     }
 
-    PCState branchTarget(const PCState &branchPC) const override;
+    std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &branch_pc) const override;
 
     // Explicitly import the otherwise hidden branchTarget.
     using StaticInst::branchTarget;
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 338ded9d14..153060ca47 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -111,8 +111,8 @@ def template MicroRegOpBranchDeclare {{
 
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        X86ISA::PCState branchTarget(
-                const X86ISA::PCState &branchPC) const override;
+        std::unique_ptr<PCStateBase> branchTarget(
+                const PCStateBase &branchPC) const override;
 
         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;
@@ -120,15 +120,16 @@ def template MicroRegOpBranchDeclare {{
 }};
 
 def template MicroRegOpBranchTarget {{
-    X86ISA::PCState
-    %(class_name)s::branchTarget(const X86ISA::PCState &branchPC) const
+    std::unique_ptr<PCStateBase>
+    %(class_name)s::branchTarget(const PCStateBase &branch_pc) const
     {
-        X86ISA::PCState pcs = branchPC;
+        PCStateBase *pcs = branch_pc.clone();
         DPRINTF(X86, "branchTarget PC info: %s, Immediate (imm8): %lx\n",
-                pcs, (int8_t)imm8);
-        pcs.npc(pcs.npc() + (int8_t)imm8);
-        pcs.uEnd();
-        return pcs;
+                *pcs, (int8_t)imm8);
+        auto &xpc = pcs->as<PCState>();
+        xpc.npc(xpc.npc() + (int8_t)imm8);
+        xpc.uEnd();
+        return std::unique_ptr<PCStateBase>{pcs};
     }
 }};
 
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index e42d888dc0..1c8ce63dd4 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -51,15 +51,16 @@ def template BrDeclare {{
 
         Fault execute(ExecContext *, Trace::InstRecord *) const override;
 
-        X86ISA::PCState
-        branchTarget(const X86ISA::PCState &branchPC) const override
+        std::unique_ptr<PCStateBase>
+        branchTarget(const PCStateBase &branch_pc) const override
         {
-            X86ISA::PCState pcs = branchPC;
+            PCStateBase *pcs = branch_pc.clone();
             DPRINTF(X86, "Br branchTarget PC info: %s, Target: %d\n",
-                    pcs, (int16_t)target);
-            pcs.nupc(target);
-            pcs.uAdvance();
-            return pcs;
+                    *pcs, (int16_t)target);
+            auto &xpc = pcs->as<PCState>();
+            xpc.nupc(target);
+            xpc.uAdvance();
+            return std::unique_ptr<PCStateBase>{pcs};
         }
 
         /// Explicitly import the otherwise hidden branchTarget
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index b9a69dcb3e..64b542d87a 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -29,6 +29,7 @@
 #include "cpu/nop_static_inst.hh"
 
 #include "arch/pcstate.hh"
+#include "config/the_isa.hh"
 #include "cpu/static_inst.hh"
 
 namespace gem5
diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 21bac40d4c..5a275738c9 100644
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -292,7 +292,7 @@ Decode::squash(const DynInstPtr &inst, ThreadID tid)
     toFetch->decodeInfo[tid].mispredictInst = inst;
     toFetch->decodeInfo[tid].squash = true;
     toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
-    toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
+    set(toFetch->decodeInfo[tid].nextPC, *inst->branchTarget());
 
     // Looking at inst->pcState().branching()
     // may yield unexpected results if the branch
@@ -715,21 +715,21 @@ Decode::decodeInsts(ThreadID tid)
         {
             ++stats.branchResolved;
 
-            if (!(inst->branchTarget() == inst->readPredTarg())) {
+            if (*inst->branchTarget() != inst->readPredTarg()) {
                 ++stats.branchMispred;
 
                 // Might want to set some sort of boolean and just do
                 // a check at the end
                 squash(inst, inst->threadNumber);
-                TheISA::PCState target = inst->branchTarget();
+                std::unique_ptr<PCStateBase> target = inst->branchTarget();
 
                 DPRINTF(Decode,
                         "[tid:%i] [sn:%llu] "
                         "Updating predictions: Wrong predicted target: %s \
                         PredPC: %s\n",
-                        tid, inst->seqNum, inst->readPredTarg(), target);
+                        tid, inst->seqNum, inst->readPredTarg(), *target);
                 //The micro pc after an instruction level branch should be 0
-                inst->setPredTarg(target);
+                inst->setPredTarg(target->as<TheISA::PCState>());
                 break;
             }
         }
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 0692ded2d3..38815b1d42 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -717,7 +717,7 @@ class DynInst : public ExecContext, public RefCounted
     OpClass opClass() const { return staticInst->opClass(); }
 
     /** Returns the branch target address. */
-    TheISA::PCState
+    std::unique_ptr<PCStateBase>
     branchTarget() const
     {
         return staticInst->branchTarget(pc);
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index 1580759167..63a8a7ae7b 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -40,14 +40,14 @@ StaticInst::fetchMicroop(MicroPC upc) const
           "that is not microcoded.");
 }
 
-TheISA::PCState
-StaticInst::branchTarget(const TheISA::PCState &pc) const
+std::unique_ptr<PCStateBase>
+StaticInst::branchTarget(const PCStateBase &pc) const
 {
     panic("StaticInst::branchTarget() called on instruction "
           "that is not a PC-relative branch.");
 }
 
-TheISA::PCState
+std::unique_ptr<PCStateBase>
 StaticInst::branchTarget(ThreadContext *tc) const
 {
     panic("StaticInst::branchTarget() called on instruction "
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 9b5fd385cd..1213eeb797 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -47,10 +47,9 @@
 #include <memory>
 #include <string>
 
-#include "arch/pcstate.hh"
+#include "arch/generic/pcstate.hh"
 #include "base/logging.hh"
 #include "base/refcnt.hh"
-#include "config/the_isa.hh"
 #include "cpu/op_class.hh"
 #include "cpu/reg_class.hh"
 #include "cpu/static_inst_fwd.hh"
@@ -339,7 +338,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
      * should be true).
      */
-    virtual TheISA::PCState branchTarget(const TheISA::PCState &pc) const;
+    virtual std::unique_ptr<PCStateBase> branchTarget(
+            const PCStateBase &pc) const;
 
     /**
      * Return the target address for an indirect branch (jump).  The
@@ -348,7 +348,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
      * execute the branch in question.  Invalid if not an indirect
      * branch (i.e. isIndirectCtrl() should be true).
      */
-    virtual TheISA::PCState branchTarget(ThreadContext *tc) const;
+    virtual std::unique_ptr<PCStateBase> branchTarget(
+            ThreadContext *tc) const;
 
     /**
      * Return string representation of disassembled instruction.