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arch-arm: Crypto instructions checking release object

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Check directly if extension is enabled instead of looking
for ID register field value. This makes the code more readable

Change-Id: If0b882ac3464c3587731b72a7edb3b8b65ea86c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-02-02 08:55:48 +00:00
parent ea3face87b
commit ebef2fc4b1
2 changed files with 22 additions and 12 deletions
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17
src/arch/arm/isa/insts/crypto.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
//
// Copyright (c) 2018 ARM Limited
// Copyright (c) 2018, 2024 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -38,8 +38,7 @@
let {{
cryptoEnabledCheckCode = '''
auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_ISAR5);
if (!(crypto_reg & %(mask)d)) {
if (!HaveExt(xc->tcBase(), %(extension)s)) {
return std::make_shared<UndefinedInstruction>(machInst, true);
}
'''
@@ -150,7 +149,9 @@ let {{
sha256_su0Code = "crypto.sha256Su0(output, input);"
sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
aes_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_AES"
}
cryptoRegRegRegInst("aese", "AESE", "SimdAesOp",
aes_enabled, aeseCode)
cryptoRegRegRegInst("aesd", "AESD", "SimdAesOp",
@@ -160,7 +161,9 @@ let {{
cryptoRegRegInst("aesimc", "AESIMC", "SimdAesMixOp",
aes_enabled, aesimcCode)
sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
sha1_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_SHA1"
}
cryptoRegRegRegInst("sha1c", "SHA1C", "SimdSha1HashOp",
sha1_enabled, sha1_cCode)
cryptoRegRegRegInst("sha1p", "SHA1P", "SimdSha1HashOp",
@@ -174,7 +177,9 @@ let {{
cryptoRegRegInst("sha1su1", "SHA1SU1", "SimdShaSigma2Op",
sha1_enabled, sha1_su1Code)
sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 }
sha2_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_SHA256"
}
cryptoRegRegRegInst("sha256h", "SHA256H", "SimdSha256HashOp",
sha2_enabled, sha256_hCode)
cryptoRegRegRegInst("sha256h2", "SHA256H2", "SimdSha256Hash2Op",

17
src/arch/arm/isa/insts/crypto64.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
//
// Copyright (c) 2018 ARM Limited
// Copyright (c) 2018, 2024 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -41,8 +41,7 @@ let {{
exec_output = ""
cryptoEnabledCheckCode = '''
auto crypto_reg = xc->tcBase()->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
if (!(crypto_reg & %(mask)d)) {
if (!HaveExt(xc->tcBase(), %(extension)s)) {
return std::make_shared<UndefinedInstruction>(machInst, true);
}
'''
@@ -133,7 +132,9 @@ let {{
sha256_su0Code = "crypto.sha256Su0(output, input);"
sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
aes_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_AES"
}
cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp",
aes_enabled, aeseCode)
cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp",
@@ -143,7 +144,9 @@ let {{
cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp",
aes_enabled, aesimcCode)
sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
sha1_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_SHA1"
}
cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp",
sha1_enabled, sha1_cCode)
cryptoRegRegRegInst("sha1p", "SHA1P64", "SimdSha1HashOp",
@@ -157,7 +160,9 @@ let {{
cryptoRegRegInst("sha1su1", "SHA1SU164", "SimdShaSigma2Op",
sha1_enabled, sha1_su1Code)
sha2_enabled = cryptoEnabledCheckCode % { "mask" : 0xF000 }
sha2_enabled = cryptoEnabledCheckCode % {
"extension" : "ArmExtension::FEAT_SHA256"
}
cryptoRegRegRegInst("sha256h", "SHA256H64", "SimdSha256HashOp",
sha2_enabled, sha256_hCode)
cryptoRegRegRegInst("sha256h2", "SHA256H264", "SimdSha256Hash2Op",