arch-riscv: Move standard ops out of ISA

This patch removes static portions of the standard instruction types
from the generated ISA code and puts them into arch/riscv/insts. Some
dynamically-generated content is left behind for each individual
instruction's implementation. Also, BranchOp is removed due to its
similarity with ImmOp and ImmOp and UImmOp are joined into a single
templated class, ImmOp<T>.

Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a
Reviewed-on: https://gem5-review.googlesource.com/6022
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

src/arch/riscv/insts/SConscript

@@ -1,4 +1,5 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'riscv':
+    Source('standard.cc')
     Source('static_inst.cc')

src/arch/riscv/insts/bitfields.hh

@@ -0,0 +1,9 @@
+#ifndef __ARCH_RISCV_BITFIELDS_HH__
+#define __ARCH_RISCV_BITFIELDS_HH__
+
+#include "base/bitfield.hh"
+
+#define CSRIMM  bits(machInst, 19, 15)
+#define FUNCT12 bits(machInst, 31, 20)
+
+#endif // __ARCH_RISCV_BITFIELDS_HH__

src/arch/riscv/insts/standard.cc

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#include "arch/riscv/insts/standard.hh"
+
+#include <sstream>
+#include <string>
+
+#include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/utility.hh"
+#include "cpu/static_inst.hh"
+
+using namespace std;
+
+namespace RiscvISA
+{
+
+string
+RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
+        registerName(_srcRegIdx[0]) << ", " <<
+        registerName(_srcRegIdx[1]);
+    return ss.str();
+}
+
+string
+CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+    stringstream ss;
+    ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
+    if (_numSrcRegs > 0)
+        ss << registerName(_srcRegIdx[0]) << ", ";
+    ss << MiscRegNames.at(csr);
+    return ss.str();
+}
+
+}

src/arch/riscv/insts/standard.hh

@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015 RISC-V Foundation
+ * Copyright (c) 2017 The University of Virginia
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Alec Roelke
+ */
+
+#ifndef __ARCH_RISCV_STANDARD_INST_HH__
+#define __ARCH_RISCV_STANDARD_INST_HH__
+
+#include <string>
+
+#include "arch/riscv/insts/bitfields.hh"
+#include "arch/riscv/insts/static_inst.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/static_inst.hh"
+
+namespace RiscvISA
+{
+
+/**
+ * Base class for operations that work only on registers
+ */
+class RegOp : public RiscvStaticInst
+{
+  protected:
+    using RiscvStaticInst::RiscvStaticInst;
+
+    std::string generateDisassembly(
+        Addr pc, const SymbolTable *symtab) const override;
+};
+
+/**
+ * Base class for operations with immediates (I is the type of immediate)
+ */
+template<typename I>
+class ImmOp : public RiscvStaticInst
+{
+  protected:
+    I imm;
+
+    ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
+    {}
+};
+
+/**
+ * Base class for system operations
+ */
+class SystemOp : public RiscvStaticInst
+{
+  protected:
+    using RiscvStaticInst::RiscvStaticInst;
+
+    std::string
+    generateDisassembly(Addr pc, const SymbolTable *symtab) const override
+    {
+        return mnemonic;
+    }
+};
+
+/**
+ * Base class for CSR operations
+ */
+class CSROp : public RiscvStaticInst
+{
+  protected:
+    uint64_t csr;
+    uint64_t uimm;
+
+    /// Constructor
+    CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
+        : RiscvStaticInst(mnem, _machInst, __opClass),
+            csr(FUNCT12), uimm(CSRIMM)
+    {}
+
+    std::string generateDisassembly(
+        Addr pc, const SymbolTable *symtab) const override;
+};
+
+}
+
+#endif // __ARCH_RISCV_STANDARD_INST_HH__

src/arch/riscv/isa/formats/compressed.isa

@@ -67,7 +67,7 @@ def format CROp(code, *opt_flags) {{
 
 def format CIOp(imm_code, code, *opt_flags) {{
     regs = ['_destRegIdx[0]','_srcRegIdx[0]']
-    iop = InstObjParams(name, Name, 'ImmOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = ImmDeclare.subst(iop)
@@ -78,7 +78,7 @@ def format CIOp(imm_code, code, *opt_flags) {{
 
 def format CUIOp(imm_code, code, *opt_flags) {{
     regs = ['_destRegIdx[0]','_srcRegIdx[0]']
-    iop = InstObjParams(name, Name, 'UImmOp',
+    iop = InstObjParams(name, Name, 'ImmOp<uint64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = ImmDeclare.subst(iop)

src/arch/riscv/isa/formats/standard.isa

@@ -33,147 +33,6 @@
 //
 // Integer instructions
 //
-output header {{
-    /**
-     * Base class for operations that work only on registers
-     */
-    class RegOp : public RiscvStaticInst
-    {
-      protected:
-        /// Constructor
-        RegOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass)
-        {}
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-
-    /**
-     * Base class for operations with signed immediates
-     */
-    class ImmOp : public RiscvStaticInst
-    {
-      protected:
-        int64_t imm;
-
-        /// Constructor
-        ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
-        {}
-
-        virtual std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
-    };
-
-    /**
-     * Base class for operations with unsigned immediates
-     */
-    class UImmOp : public RiscvStaticInst
-    {
-      protected:
-        uint64_t imm;
-
-        /// Constructor
-        UImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass), imm(0)
-        {}
-
-        virtual std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
-    };
-
-    /**
-     * Base class for operations with branching
-     */
-    class BranchOp : public ImmOp
-    {
-      protected:
-        /// Constructor
-        BranchOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : ImmOp(mnem, _machInst, __opClass)
-        {}
-
-        using StaticInst::branchTarget;
-
-        virtual RiscvISA::PCState
-        branchTarget(ThreadContext *tc) const
-        {
-            return StaticInst::branchTarget(tc);
-        }
-
-        virtual RiscvISA::PCState
-        branchTarget(const RiscvISA::PCState &branchPC) const
-        {
-            return StaticInst::branchTarget(branchPC);
-        }
-
-        virtual std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
-    };
-
-    /**
-     * Base class for system operations
-     */
-    class SystemOp : public RiscvStaticInst
-    {
-      public:
-        /// Constructor
-        SystemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass)
-        {}
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const
-        {
-            return mnemonic;
-        }
-    };
-
-    /**
-     * Base class for CSR operations
-     */
-    class CSROp : public RiscvStaticInst
-    {
-      protected:
-        uint64_t csr;
-        uint64_t uimm;
-
-      public:
-        /// Constructor
-        CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
-            : RiscvStaticInst(mnem, _machInst, __opClass),
-              csr(FUNCT12), uimm(CSRIMM)
-        {}
-
-        std::string
-        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-    };
-}};
-
-//Outputs to decoder.cc
-output decoder {{
-    std::string
-    RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        std::stringstream ss;
-        ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
-            registerName(_srcRegIdx[0]) << ", " <<
-            registerName(_srcRegIdx[1]);
-        return ss.str();
-    }
-
-    std::string
-    CSROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
-    {
-        std::stringstream ss;
-        ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
-        if (_numSrcRegs > 0)
-            ss << registerName(_srcRegIdx[0]) << ", ";
-        ss << MiscRegNames.at(csr);
-        return ss.str();
-    }
-}};
 
 def template ImmDeclare {{
     //
@@ -362,7 +221,7 @@ def format ROp(code, *opt_flags) {{
 def format IOp(code, *opt_flags) {{
     imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
     regs = ['_destRegIdx[0]','_srcRegIdx[0]']
-    iop = InstObjParams(name, Name, 'ImmOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = ImmDeclare.subst(iop)
@@ -380,7 +239,7 @@ def format BOp(code, *opt_flags) {{
                     imm |= ~((uint64_t)0xFFF);
                """
     regs = ['_srcRegIdx[0]','_srcRegIdx[1]']
-    iop = InstObjParams(name, Name, 'BranchOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = BranchDeclare.subst(iop)
@@ -392,7 +251,7 @@ def format BOp(code, *opt_flags) {{
 def format Jump(code, *opt_flags) {{
     imm_code = 'imm = IMM12; if (IMMSIGN > 0) imm |= ~((uint64_t)0x7FF);'
     regs = ['_destRegIdx[0]','_srcRegIdx[0]']
-    iop = InstObjParams(name, Name, 'BranchOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = JumpDeclare.subst(iop)
@@ -404,7 +263,7 @@ def format Jump(code, *opt_flags) {{
 def format UOp(code, *opt_flags) {{
     imm_code = 'imm = (int32_t)(IMM20 << 12);'
     regs = ['_destRegIdx[0]']
-    iop = InstObjParams(name, Name, 'ImmOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = ImmDeclare.subst(iop)
@@ -423,7 +282,7 @@ def format JOp(code, *opt_flags) {{
                """
     pc = 'pc.set(pc.pc() + imm);'
     regs = ['_destRegIdx[0]']
-    iop = InstObjParams(name, Name, 'BranchOp',
+    iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
         {'code': code, 'imm_code': imm_code,
          'regs': ','.join(regs)}, opt_flags)
     header_output = BranchDeclare.subst(iop)

src/arch/riscv/isa/includes.isa

@@ -42,6 +42,7 @@ output header {{
 #include <tuple>
 #include <vector>
 
+#include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"