arch,cpu: Make the CPU's ISA parameter type BaseISA.

This is mostly only a superficial change since the isa parameter is
then dynamic cast to the ISA specific version inside the various
consumers, currently the SimpleThread, O3CPU and Decoder classes. If
those aren't being used, for instance in the fast model CPUs, then you
can use a different ISA implementation without any type clashes.

Change-Id: I2226ef60f9a471ae51b8bfce8683033f7854197a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25009
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/BaseCPU.py

@@ -66,37 +66,30 @@ if buildEnv['TARGET_ISA'] == 'alpha':
     from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
     from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
     from m5.objects.AlphaISA import AlphaISA as ArchISA
-    ArchISAsParam = VectorParam.AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
     from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
     from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
     from m5.objects.SparcISA import SparcISA as ArchISA
-    ArchISAsParam = VectorParam.SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
     from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
     from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
     from m5.objects.X86ISA import X86ISA as ArchISA
-    ArchISAsParam = VectorParam.X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
     from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
     from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
     from m5.objects.MipsISA import MipsISA as ArchISA
-    ArchISAsParam = VectorParam.MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
     from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
     from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
     from m5.objects.ArmISA import ArmISA as ArchISA
-    ArchISAsParam = VectorParam.ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
     from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
     from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
     from m5.objects.PowerISA import PowerISA as ArchISA
-    ArchISAsParam = VectorParam.PowerISA
 elif buildEnv['TARGET_ISA'] == 'riscv':
     from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
     from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
     from m5.objects.RiscvISA import RiscvISA as ArchISA
-    ArchISAsParam = VectorParam.RiscvISA
 else:
     print("Don't know what object types to use for ISA %s" %
             buildEnv['TARGET_ISA'])
@@ -176,7 +169,7 @@ class BaseCPU(ClockedObject):
     if buildEnv['TARGET_ISA'] == 'power':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
     interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
-    isa = ArchISAsParam([], "ISA instance")
+    isa = VectorParam.BaseISA([], "ISA instance")
 
     max_insts_all_threads = Param.Counter(0,
         "terminate when all threads have reached this inst count")