derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Implement FEAT_TCR2

Browse Source 
Change-Id: I0396f5938c09b68fcc3303a6fdda1e4dde290869
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-05-11 09:53:52 +01:00
parent 49cbb24351
commit eac5a8b215
5 changed files with 105 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/arch/arm/ArmSystem.py
View File

@@ -103,6 +103,7 @@ class ArmExtension(ScopedEnum):
"FEAT_HCX",
# Armv8.9
"FEAT_SCTLR2",
"FEAT_TCR2",
# Armv9.2
"FEAT_SME", # Optional in Armv9.2
# Others
@@ -261,9 +262,7 @@ class Armv87(Armv86):
class Armv89(Armv87):
extensions = Armv87.extensions + [
"FEAT_SCTLR2",
]
extensions = Armv87.extensions + ["FEAT_SCTLR2", "FEAT_TCR2"]
class Armv92(Armv89):

2
src/arch/arm/isa.cc
View File

@@ -332,6 +332,8 @@ ISA::redirectRegVHE(int misc_reg)
return MISCREG_TTBR1_EL1;
case MISCREG_TCR_EL12:
return MISCREG_TCR_EL1;
case MISCREG_TCR2_EL12:
return MISCREG_TCR2_EL1;
case MISCREG_SPSR_EL12:
return MISCREG_SPSR_EL1;
case MISCREG_ELR_EL12:

93
src/arch/arm/regs/misc.cc
View File

@@ -996,6 +996,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
{ MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
{ MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
{ MiscRegNum64(3, 0, 2, 0, 3), MISCREG_TCR2_EL1 },
{ MiscRegNum64(3, 0, 2, 1, 0), MISCREG_APIAKeyLo_EL1 },
{ MiscRegNum64(3, 0, 2, 1, 1), MISCREG_APIAKeyHi_EL1 },
{ MiscRegNum64(3, 0, 2, 1, 2), MISCREG_APIBKeyLo_EL1 },
@@ -1155,6 +1156,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
{ MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
{ MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
{ MiscRegNum64(3, 4, 2, 0, 3), MISCREG_TCR2_EL2 },
{ MiscRegNum64(3, 4, 2, 1, 0), MISCREG_VTTBR_EL2 },
{ MiscRegNum64(3, 4, 2, 1, 2), MISCREG_VTCR_EL2 },
{ MiscRegNum64(3, 4, 2, 6, 0), MISCREG_VSTTBR_EL2 },
@@ -1235,6 +1237,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
{ MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
{ MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
{ MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
{ MiscRegNum64(3, 5, 2, 0, 3), MISCREG_TCR2_EL12 },
{ MiscRegNum64(3, 5, 4, 0, 0), MISCREG_SPSR_EL12 },
{ MiscRegNum64(3, 5, 4, 0, 1), MISCREG_ELR_EL12 },
{ MiscRegNum64(3, 5, 5, 1, 0), MISCREG_AFSR0_EL12 },
@@ -1977,6 +1980,83 @@ faultSctlr2VheEL2(const MiscRegLUTEntry &entry,
}
}
template<bool read, auto g_bitfield>
Fault
faultTcr2EL1(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
const HCRX hcrx = tc->readMiscReg(MISCREG_HCRX_EL2);
if (auto fault = faultHcrFgtEL1<read, g_bitfield, &HFGTR::tcrEL1>(entry, tc, inst);
fault != NoFault) {
return fault;
} else if (EL2Enabled(tc) && (!isHcrxEL2Enabled(tc) || !hcrx.tcr2En)) {
return inst.generateTrap(EL2);
} else if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
return inst.generateTrap(EL3);
} else {
return NoFault;
}
} else {
return inst.undefined();
}
}
Fault
faultTcr2EL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
return inst.generateTrap(EL3);
} else {
return NoFault;
}
} else {
return inst.undefined();
}
}
Fault
faultTcr2VheEL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
if (hcr.e2h) {
if (ArmSystem::haveEL(tc, EL3) && !scr.tcr2En) {
return inst.generateTrap(EL3);
} else {
return NoFault;
}
} else {
return inst.undefined();
}
} else {
return inst.undefined();
}
}
Fault
faultTcr2VheEL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
if (HaveExt(tc, ArmExtension::FEAT_TCR2)) {
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const bool el2_host = EL2Enabled(tc) && hcr.e2h;
if (el2_host) {
return NoFault;
} else {
return inst.undefined();
}
} else {
return inst.undefined();
}
}
template<bool read, auto r_bitfield>
Fault
faultCpacrEL1(const MiscRegLUTEntry &entry,
@@ -4434,6 +4514,7 @@ ISA::initializeMiscRegMetadata()
.reset([p,release=release](){
AA64MMFR3 mmfr3_el1 = 0;
mmfr3_el1.sctlrx = release->has(ArmExtension::FEAT_SCTLR2) ? 0x1 : 0x0;
mmfr3_el1.tcrx = release->has(ArmExtension::FEAT_TCR2) ? 0x1 : 0x0;
return mmfr3_el1;
}())
.faultRead(EL0, faultIdst)
@@ -4660,6 +4741,15 @@ ISA::initializeMiscRegMetadata()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_TTBCR_NS);
InitReg(MISCREG_TCR2_EL1)
.allPrivileges().exceptUserMode()
.faultRead(EL1, faultTcr2EL1<true, &HCR::trvm>)
.faultWrite(EL1, faultTcr2EL1<false, &HCR::tvm>)
.fault(EL2, faultTcr2EL2);
InitReg(MISCREG_TCR2_EL12)
.fault(EL2, faultTcr2VheEL2)
.fault(EL3, faultTcr2VheEL3)
.mapsTo(MISCREG_TCR2_EL1);
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTTBR);
@@ -4668,6 +4758,9 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TCR_EL2)
.hyp().mon()
.mapsTo(MISCREG_HTCR);
InitReg(MISCREG_TCR2_EL2)
.hyp().mon()
.fault(EL2, faultTcr2EL2);
InitReg(MISCREG_VTTBR_EL2)
.hyp().mon()
.mapsTo(MISCREG_VTTBR);

6
src/arch/arm/regs/misc.hh
View File

@@ -610,8 +610,11 @@ namespace ArmISA
MISCREG_TTBR1_EL12,
MISCREG_TCR_EL1,
MISCREG_TCR_EL12,
MISCREG_TCR2_EL1,
MISCREG_TCR2_EL12,
MISCREG_TTBR0_EL2,
MISCREG_TCR_EL2,
MISCREG_TCR2_EL2,
MISCREG_VTTBR_EL2,
MISCREG_VTCR_EL2,
MISCREG_VSTTBR_EL2,
@@ -2334,8 +2337,11 @@ namespace ArmISA
"ttbr1_el12",
"tcr_el1",
"tcr_el12",
"tcr2_el1",
"tcr2_el12",
"ttbr0_el2",
"tcr_el2",
"tcr2_el2",
"vttbr_el2",
"vtcr_el2",
"vsttbr_el2",

2
src/arch/arm/regs/misc_types.hh
View File

@@ -377,6 +377,7 @@ namespace ArmISA
BitUnion64(SCR)
Bitfield<44> sctlr2En;
Bitfield<43> tcr2En;
Bitfield<40> trndr;
Bitfield<38> hxen;
Bitfield<27> fgten;
@@ -1061,6 +1062,7 @@ namespace ArmISA
BitUnion64(HCRX)
Bitfield<15> sctlr2En;
Bitfield<14> tcr2En;
EndBitUnion(HCRX)
} // namespace ArmISA