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ext,stdlib: Update integration of DRAMSys

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The latest version of DRAMSys required several API changes which were
applied in this commit.

Also, the README for the usage of DRAMSys has been updated.

The updated version fixes a bug in DRAMSys that caused some full-system
simulations to loop endlessly.

GitHub Issue: https://github.com/gem5/gem5/issues/1452
This commit is contained in:
Derek Christ
2025-03-18 16:19:33 +01:00
parent 43fbdd853f
commit e89a9e22f5
11 changed files with 25 additions and 61 deletions
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2
configs/example/gem5_library/dramsys/arm-hello-dramsys.py
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@@ -53,7 +53,7 @@ requires(isa_required=ISA.ARM)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32KiB", l1i_size="32KiB")
# We use a single channel DDR3_1600 memory system
memory = DRAMSysDDR3_1600(recordable=True)
memory = DRAMSysDDR3_1600()
# We use a simple Timing processor with one core.
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)