ext,stdlib: Update integration of DRAMSys

The latest version of DRAMSys required several API changes which were
applied in this commit.

Also, the README for the usage of DRAMSys has been updated.

The updated version fixes a bug in DRAMSys that caused some full-system
simulations to loop endlessly.

GitHub Issue: https://github.com/gem5/gem5/issues/1452

configs/example/gem5_library/dramsys/arm-hello-dramsys.py

@@ -53,7 +53,7 @@ requires(isa_required=ISA.ARM)
 cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="32KiB", l1i_size="32KiB")
 
 # We use a single channel DDR3_1600 memory system
-memory = DRAMSysDDR3_1600(recordable=True)
+memory = DRAMSysDDR3_1600()
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.ARM, num_cores=1)

configs/example/gem5_library/dramsys/dramsys-traffic.py

@@ -39,7 +39,6 @@ from gem5.simulate.simulator import Simulator
 
 memory = DRAMSysMem(
     configuration="ext/dramsys/DRAMSys/configs/ddr4-example.json",
-    recordable=True,
     size="4GiB",
 )