Merge with main repository.

src/arch/arm/vtophys.hh

@@ -38,7 +38,6 @@
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace ArmISA {
     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }

src/arch/mips/vtophys.hh

@@ -38,7 +38,6 @@
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace MipsISA {
     Addr vtophys(Addr vaddr);

src/arch/power/vtophys.hh

@@ -40,7 +40,6 @@
 #include "arch/power/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace PowerISA {
 

src/arch/sparc/vtophys.hh

@@ -36,13 +36,9 @@
 #include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace SparcISA {
 
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 

src/cpu/inorder/thread_context.hh

@@ -44,8 +44,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the InOrderCPU.  It
  * provides the interface for any external objects to access a

src/cpu/o3/thread_context.hh

@@ -40,8 +40,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the O3CPU.  It
  * provides the interface for any external objects to access a

src/cpu/simple_thread.hh

@@ -57,8 +57,6 @@ class BaseCPU;
 
 class FunctionProfile;
 class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
 
 namespace TheISA {
     namespace Kernel {

src/kern/solaris/solaris.hh

@@ -34,8 +34,6 @@
 #include "base/types.hh"
 #include "kern/operatingsystem.hh"
 
-class TranslatingPort;
-
 ///
 /// This class encapsulates the types, structures, constants,
 /// functions, and syscall-number mappings specific to the Solaris

src/mem/ruby/system/RubyPort.cc

@@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx)
         // RubyPort should only have one port to physical memory
         assert (physMemPort == NULL);
 
-        physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
-                                 ruby_system, access_phys_mem);
+        physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
 
         return physMemPort;
     }

src/mem/ruby/system/RubyPort.hh

@@ -155,7 +155,7 @@ class RubyPort : public MemObject
     uint16_t m_port_id;
     uint64_t m_request_cnt;
 
-    M5Port* physMemPort;
+    PioPort* physMemPort;
 
     /*! Vector of CPU Port attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;