From ef9fc010736df313fbc7acaea3a9b0e2fee33955 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 03:44:25 -0500 Subject: [PATCH 1/3] MEM: Clean-up of Functional/Virtual/TranslatingPort remnants This patch cleans up forward declarations and a member-function prototype that still referred to the old FunctionalPort, VirtualPort and TranslatingPort. There is no change in functionality. --- src/arch/arm/vtophys.hh | 1 - src/arch/mips/vtophys.hh | 1 - src/arch/power/vtophys.hh | 1 - src/arch/sparc/vtophys.hh | 4 ---- src/cpu/inorder/thread_context.hh | 2 -- src/cpu/o3/thread_context.hh | 2 -- src/cpu/simple_thread.hh | 3 --- src/kern/solaris/solaris.hh | 2 -- 8 files changed, 16 deletions(-) diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh index a85209a4a0..12a6c6ec69 100644 --- a/src/arch/arm/vtophys.hh +++ b/src/arch/arm/vtophys.hh @@ -38,7 +38,6 @@ #include "arch/arm/utility.hh" class ThreadContext; -class FunctionalPort; namespace ArmISA { inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh index 5ecc30b1f1..741ac36bc4 100644 --- a/src/arch/mips/vtophys.hh +++ b/src/arch/mips/vtophys.hh @@ -38,7 +38,6 @@ #include "arch/mips/utility.hh" class ThreadContext; -class FunctionalPort; namespace MipsISA { inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh index 7371f38a6b..1e8caf8032 100644 --- a/src/arch/power/vtophys.hh +++ b/src/arch/power/vtophys.hh @@ -40,7 +40,6 @@ #include "arch/power/utility.hh" class ThreadContext; -class FunctionalPort; namespace PowerISA { diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh index f55967b538..7c1d23e808 100644 --- a/src/arch/sparc/vtophys.hh +++ b/src/arch/sparc/vtophys.hh @@ -36,13 +36,9 @@ #include "arch/sparc/pagetable.hh" class ThreadContext; -class FunctionalPort; namespace SparcISA { -PageTableEntry -kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr); - Addr vtophys(Addr vaddr); Addr vtophys(ThreadContext *tc, Addr vaddr); diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh index 5b67d7e8b2..058f58ffbf 100644 --- a/src/cpu/inorder/thread_context.hh +++ b/src/cpu/inorder/thread_context.hh @@ -44,8 +44,6 @@ namespace Kernel { class Statistics; }; -class TranslatingPort; - /** * Derived ThreadContext class for use with the InOrderCPU. It * provides the interface for any external objects to access a diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 6ac7457707..0205c63efd 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -40,8 +40,6 @@ namespace Kernel { class Statistics; }; -class TranslatingPort; - /** * Derived ThreadContext class for use with the O3CPU. It * provides the interface for any external objects to access a diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index ebc23276af..57e83b4d13 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -58,8 +58,6 @@ class BaseCPU; class FunctionProfile; class ProfileNode; -class FunctionalPort; -class PhysicalPort; namespace TheISA { namespace Kernel { @@ -71,7 +69,6 @@ namespace TheISA { #include "mem/page_table.hh" #include "sim/process.hh" -class TranslatingPort; #endif // FULL_SYSTEM diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh index 00eee994b5..c6fb93f04a 100644 --- a/src/kern/solaris/solaris.hh +++ b/src/kern/solaris/solaris.hh @@ -42,8 +42,6 @@ class Solaris {}; #include "kern/operatingsystem.hh" -class TranslatingPort; - /// /// This class encapsulates the types, structures, constants, /// functions, and syscall-number mappings specific to the Solaris From cfc268ad9e5b83cac551cae118811e5c86382d9e Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 05:38:24 -0500 Subject: [PATCH 2/3] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system. --- src/mem/ruby/system/RubyPort.cc | 3 +-- src/mem/ruby/system/RubyPort.hh | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index b60ca2a073..af414f17ac 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx) // RubyPort should only have one port to physical memory assert (physMemPort == NULL); - physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, - ruby_system, access_phys_mem); + physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this); return physMemPort; } diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 2ffdef3d9d..6df713a13a 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -155,7 +155,7 @@ class RubyPort : public MemObject uint16_t m_port_id; uint64_t m_request_cnt; - M5Port* physMemPort; + PioPort* physMemPort; /*! Vector of CPU Port attached to this Ruby port. */ typedef std::vector::iterator CpuPortIter; From ade53def9252a36a39b2c4bd61196355906f0505 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 30 Jan 2012 09:37:06 -0500 Subject: [PATCH 3/3] Ruby: Connect system port in Ruby network test This patch moves the connection of the system port to create_system in Ruby.py. Thereby it allows the failing Ruby test (and other Ruby systems) to run again. --- configs/example/se.py | 1 - configs/ruby/Ruby.py | 5 ++++- tests/configs/memtest-ruby.py | 4 ---- tests/configs/o3-timing-mp-ruby.py | 2 ++ tests/configs/o3-timing-ruby.py | 3 +++ tests/configs/rubytest-ruby.py | 3 --- tests/configs/simple-atomic-mp-ruby.py | 2 ++ tests/configs/simple-timing-mp-ruby.py | 3 --- tests/configs/simple-timing-ruby.py | 3 --- 9 files changed, 11 insertions(+), 15 deletions(-) diff --git a/configs/example/se.py b/configs/example/se.py index 5723644824..b94652ac0c 100644 --- a/configs/example/se.py +++ b/configs/example/se.py @@ -184,7 +184,6 @@ if options.ruby: options.use_map = True Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) - system.system_port = system.ruby._sys_port_proxy.port else: system.system_port = system.membus.port system.physmem.port = system.membus.port diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py index b2342eed49..920eac0192 100644 --- a/configs/ruby/Ruby.py +++ b/configs/ruby/Ruby.py @@ -105,6 +105,10 @@ def create_system(options, system, piobus = None, dma_devices = []): # full-fledged controller system.sys_port_proxy = sys_port_proxy + # Connect the system port for loading of binaries etc + system.system_port = system.sys_port_proxy.port + + # # Set the network classes based on the command line options # @@ -182,5 +186,4 @@ def create_system(options, system, piobus = None, dma_devices = []): ruby.profiler = ruby_profiler ruby.mem_size = total_mem_size ruby._cpu_ruby_ports = cpu_sequencers - ruby._sys_port_proxy = sys_port_proxy ruby.random_seed = options.random_seed diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py index 2517e76707..49f1520179 100644 --- a/tests/configs/memtest-ruby.py +++ b/tests/configs/memtest-ruby.py @@ -109,10 +109,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports): # ruby_port.access_phys_mem = False - -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py index b14f0e5b1f..6f01167d34 100644 --- a/tests/configs/o3-timing-mp-ruby.py +++ b/tests/configs/o3-timing-mp-ruby.py @@ -46,6 +46,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py index 07851ae9f1..3b6d58b3b9 100644 --- a/tests/configs/o3-timing-ruby.py +++ b/tests/configs/o3-timing-ruby.py @@ -43,4 +43,7 @@ system = System(cpu = cpu, system.physmem.port = system.membus.port cpu.connectAllPorts(system.membus) +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port + root = Root(system = system) diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py index a7e598b0ae..b63833ccf6 100644 --- a/tests/configs/rubytest-ruby.py +++ b/tests/configs/rubytest-ruby.py @@ -105,9 +105,6 @@ for ruby_port in system.ruby._cpu_ruby_ports: # ruby_port.access_phys_mem = False -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py index 705f13ef39..f8a7b1d178 100644 --- a/tests/configs/simple-atomic-mp-ruby.py +++ b/tests/configs/simple-atomic-mp-ruby.py @@ -47,6 +47,8 @@ for cpu in cpus: # connect memory to membus system.physmem.port = system.membus.port +# Connect the system port for loading of binaries etc +system.system_port = system.membus.port # ----------------------- # run simulation diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py index 58ca862e18..d57ccea150 100644 --- a/tests/configs/simple-timing-mp-ruby.py +++ b/tests/configs/simple-timing-mp-ruby.py @@ -88,9 +88,6 @@ for (i, cpu) in enumerate(system.cpu): cpu.icache_port = system.ruby._cpu_ruby_ports[i].port cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # ----------------------- diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py index 359421a49d..1d67f6f976 100644 --- a/tests/configs/simple-timing-ruby.py +++ b/tests/configs/simple-timing-ruby.py @@ -85,9 +85,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1) cpu.icache_port = system.ruby._cpu_ruby_ports[0].port cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port -# Connect the system port for loading of binaries etc -system.system_port = system.ruby._sys_port_proxy.port - # ----------------------- # run simulation # -----------------------