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stdlib: Use newly defined tree for PrivateL1PrivateL2 hierarchy

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Change-Id: I803c6118c4df62484018f9e4d995026adb1bbc2c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-03-18 09:33:42 +00:00
committed by Pranith Kumar
parent d67672facc
commit e6637fc852
1 changed files with 18 additions and 21 deletions
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39
src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py
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@@ -127,35 +127,29 @@ class PrivateL1PrivateL2CacheHierarchy(
for _, port in board.get_memory().get_mem_ports():
self.membus.mem_side_ports = port
self.l1icaches = [
L1ICache(size=self._l1i_size)
for i in range(board.get_processor().get_num_cores())
]
self.l1dcaches = [
L1DCache(size=self._l1d_size)
for i in range(board.get_processor().get_num_cores())
]
self.l2buses = [
L2XBar() for i in range(board.get_processor().get_num_cores())
]
self.l2caches = [
L2Cache(size=self._l2_size)
for i in range(board.get_processor().get_num_cores())
]
if board.has_coherent_io():
self._setup_io_cache(board)
for i, cpu in enumerate(board.get_processor().get_cores()):
cpu.connect_icache(self.l1icaches[i].cpu_side)
cpu.connect_dcache(self.l1dcaches[i].cpu_side)
l2_node = self.add_root_child(
f"l2-cache-{i}", L2Cache(size=self._l2_size)
)
l1i_node = l2_node.add_child(
f"l1i-cache-{i}", L1ICache(size=self._l1i_size)
)
l1d_node = l2_node.add_child(
f"l1d-cache-{i}", L1DCache(size=self._l1d_size)
)
self.l1icaches[i].mem_side = self.l2buses[i].cpu_side_ports
self.l1dcaches[i].mem_side = self.l2buses[i].cpu_side_ports
self.l2buses[i].mem_side_ports = l2_node.cache.cpu_side
self.membus.cpu_side_ports = l2_node.cache.mem_side
self.l2buses[i].mem_side_ports = self.l2caches[i].cpu_side
l1i_node.cache.mem_side = self.l2buses[i].cpu_side_ports
l1d_node.cache.mem_side = self.l2buses[i].cpu_side_ports
self.membus.cpu_side_ports = self.l2caches[i].mem_side
cpu.connect_icache(l1i_node.cache.cpu_side)
cpu.connect_dcache(l1d_node.cache.cpu_side)
self._connect_table_walker(i, cpu)
@@ -166,6 +160,9 @@ class PrivateL1PrivateL2CacheHierarchy(
else:
cpu.connect_interrupt()
if board.has_coherent_io():
self._setup_io_cache(board)
def _connect_table_walker(self, cpu_id: int, cpu: BaseCPU) -> None:
cpu.connect_walker_ports(
self.membus.cpu_side_ports, self.membus.cpu_side_ports