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arch,cpu,sim: Store registers in InstRecord with InstResult.

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The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-09-11 04:19:55 -07:00
parent 81e07670b9
commit e425bcabd2
8 changed files with 55 additions and 65 deletions
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17
src/cpu/exetrace.cc
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@@ -115,18 +115,11 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
outs << "Predicated False";
}
if (debug::ExecResult && data_status != DataInvalid) {
switch (data_status) {
case DataVec:
ccprintf(outs, " D=%s", *data.as_vec);
break;
case DataVecPred:
ccprintf(outs, " D=%s", *data.as_pred);
break;
default:
ccprintf(outs, " D=%#018x", data.as_int);
break;
}
if (debug::ExecResult && dataStatus != DataInvalid) {
if (dataStatus == DataReg)
ccprintf(outs, " D=%s", data.asReg.asString());
else
ccprintf(outs, " D=%#018x", data.asInt);
}
if (debug::ExecEffAddr && getMemValid())