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arch,cpu,sim: Store registers in InstRecord with InstResult.

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The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-09-11 04:19:55 -07:00
parent 81e07670b9
commit e425bcabd2
8 changed files with 55 additions and 65 deletions
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8
src/arch/isa_parser/operand_types.py
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@@ -229,7 +229,7 @@ class RegValOperand(RegOperand):
RegVal final_val = {reg_val};
xc->setRegOperand(this, {self.dest_reg_idx}, final_val);
if (traceData) {{
traceData->setData(final_val);
traceData->setData({self.reg_class}, final_val);
}}
}}'''
@@ -354,7 +354,7 @@ class VecRegOperand(RegOperand):
def makeWrite(self):
return f'''
if (traceData) {{
traceData->setData(tmp_d{self.dest_reg_idx});
traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
}}
'''
@@ -398,7 +398,7 @@ class VecPredRegOperand(RegOperand):
def makeWrite(self):
return f'''
if (traceData) {{
traceData->setData(tmp_d{self.dest_reg_idx});
traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
}}
'''
@@ -447,7 +447,7 @@ class ControlRegOperand(Operand):
f'{self.dest_reg_idx}, {self.base_name});\n'
wb += f'''
if (traceData) {{
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
}}
'''