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arch,cpu,sim: Store registers in InstRecord with InstResult.

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The InstResult knows how to print registers without having to know about
their actual types.

Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
This commit is contained in:
Gabe Black
2021-09-11 04:19:55 -07:00
parent 81e07670b9
commit e425bcabd2
8 changed files with 55 additions and 65 deletions
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4
src/arch/arm/insts/tme64ruby.cc
View File

@@ -126,7 +126,7 @@ Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
uint64_t final_val = Dest64;
if (traceData) { traceData->setData(final_val); }
if (traceData) { traceData->setData(intRegClass, final_val); }
}
return fault;
@@ -156,7 +156,7 @@ Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
if (fault == NoFault) {
uint64_t final_val = Dest64;
xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
if (traceData) { traceData->setData(final_val); }
if (traceData) { traceData->setData(intRegClass, final_val); }
}
return fault;

14
src/arch/arm/isa/operands.isa
View File

@@ -123,7 +123,7 @@ let {{
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
class PIntReg(IntReg):
@@ -148,7 +148,7 @@ let {{
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
class IntRegAIWPC(IntReg):
@@ -165,7 +165,7 @@ let {{
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
{"}"}
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
class IntReg64(IntRegOp):
@@ -186,7 +186,7 @@ let {{
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(intWidth));
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
def __init__(self, idx, id=srtNormal):
super().__init__('ud', idx, 'IsInteger', id)
@@ -205,7 +205,7 @@ let {{
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(aarch64 ? 64 : 32));
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
class IntRegW64(IntReg64):
@@ -222,7 +222,7 @@ let {{
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(32));
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
class CCReg(CCRegOp):
@@ -248,7 +248,7 @@ let {{
xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()),
{self.base_name});
if (traceData)
traceData->setData({self.base_name});
traceData->setData({self.reg_class}, {self.base_name});
'''
def __init__(self, idx, id=srtNormal, ctype='uw'):
super().__init__(idx, id, ctype, (None, None, 'IsControl'))