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X86: Start implementing segmentation support.

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Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.

--HG--
extra : convert_revision : be5a3b33d33f243ed6e1ad63faea8495e46d0ac9
This commit is contained in:
Gabe Black
2007-08-04 20:12:54 -07:00
parent ced6cbcccf
commit e410a925df
29 changed files with 516 additions and 534 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/arch/x86/emulenv.cc
View File

@@ -88,5 +88,18 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
}
}
}
//Figure out what segment to use. This won't be entirely accurate since
//the presence of a displacement is supposed to make the instruction
//default to the data segment.
if (base != INTREG_RBP && base != INTREG_RSP ||
0/*Has an immediate offset*/) {
seg = SEGMENT_REG_DS;
//Handle any segment override that might have been in the instruction
int segFromInst = machInst.legacy.seg;
if (segFromInst)
seg = (SegmentRegIndex)(segFromInst - 1);
} else {
seg = SEGMENT_REG_SS;
}
}

6
src/arch/x86/emulenv.hh
View File

@@ -58,8 +58,9 @@
#ifndef __ARCH_X86_EMULENV_HH__
#define __ARCH_X86_EMULENV_HH__
#include "arch/x86/types.hh"
#include "arch/x86/intregs.hh"
#include "arch/x86/segmentregs.hh"
#include "arch/x86/types.hh"
namespace X86ISA
{
@@ -67,6 +68,7 @@ namespace X86ISA
{
RegIndex reg;
RegIndex regm;
SegmentRegIndex seg;
uint8_t scale;
RegIndex index;
RegIndex base;
@@ -76,7 +78,7 @@ namespace X86ISA
EmulEnv(RegIndex _reg, RegIndex _regm,
int _dataSize, int _addressSize, int _stackSize) :
reg(_reg), regm(_regm),
reg(_reg), regm(_regm), seg(SEGMENT_REG_DS),
scale(0), index(NUM_INTREGS),
base(NUM_INTREGS),
dataSize(_dataSize), addressSize(_addressSize),

88
src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
View File

@@ -68,45 +68,45 @@ def macroop ADD_R_I
def macroop ADD_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ADD_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ADD_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ADD_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ADD_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADD_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
@@ -123,47 +123,47 @@ def macroop SUB_R_I
def macroop SUB_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SUB_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SUB_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SUB_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SUB_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ADC_R_R
@@ -180,45 +180,45 @@ def macroop ADC_R_I
def macroop ADC_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ADC_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ADC_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ADC_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ADC_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop ADC_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
@@ -235,47 +235,47 @@ def macroop SBB_R_I
def macroop SBB_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};
def macroop SBB_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SBB_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SBB_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SBB_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop NEG_R
@@ -285,16 +285,16 @@ def macroop NEG_R
def macroop NEG_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop NEG_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
'''

20
src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
View File

@@ -61,17 +61,17 @@ def macroop INC_R
def macroop INC_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop INC_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
addi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
st t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
addi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, riprel, disp
};
def macroop DEC_R
@@ -81,16 +81,16 @@ def macroop DEC_R
def macroop DEC_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop DEC_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
subi reg, reg, 1, flags=(OF, SF, ZF, AF, PF)
st t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
subi t1, t1, 1, flags=(OF, SF, ZF, AF, PF)
st t1, seg, riprel, disp
};
'''

38
src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
View File

@@ -66,14 +66,14 @@ def macroop MUL_B_R
def macroop MUL_B_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mul1u rax, rax, t1, dataSize="2"
};
def macroop MUL_B_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, riprel, disp
mul1u rax, rax, t1, dataSize="2"
};
@@ -89,7 +89,7 @@ def macroop MUL_R
def macroop MUL_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
muleh rdx, rax, t1
mulel rax, rax, t1
};
@@ -97,7 +97,7 @@ def macroop MUL_M
def macroop MUL_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, riprel, disp
muleh rdx, rax, t1
mulel rax, rax, t1
};
@@ -113,14 +113,14 @@ def macroop IMUL_B_R
def macroop IMUL_B_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mul1s rax, rax, t1, dataSize="2"
};
def macroop IMUL_B_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, riprel, disp
mul1s rax, rax, t1, dataSize="2"
};
@@ -136,7 +136,7 @@ def macroop IMUL_R
def macroop IMUL_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
muleh rdx, rax, t1
mulel rax, rax, t1
};
@@ -144,7 +144,7 @@ def macroop IMUL_M
def macroop IMUL_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, riprel, disp
muleh rdx, rax, t1
mulel rax, rax, t1
};
@@ -161,14 +161,14 @@ def macroop IMUL_R_R
def macroop IMUL_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mulel reg, reg, t1
};
def macroop IMUL_R_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, riprel, disp
mulel reg, reg, t1
};
@@ -185,7 +185,7 @@ def macroop IMUL_R_R_I
def macroop IMUL_R_M_I
{
limm t1, imm
ld t2, ds, [scale, index, base], disp
ld t2, seg, sib, disp
mulel reg, t2, t1
};
@@ -193,7 +193,7 @@ def macroop IMUL_R_P_I
{
rdip t7
limm t1, imm
ld t2, ds, [0, t0, t7]
ld t2, seg, riprel
mulel reg, t2, t1
};
@@ -208,14 +208,14 @@ def macroop DIV_B_R
def macroop DIV_B_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
div1 rax, rax, t1
};
def macroop DIV_B_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
div1 rax, rax, t1
};
@@ -231,7 +231,7 @@ def macroop DIV_R
def macroop DIV_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
divr rdx, rax, t1
divq rax, rax, t1
};
@@ -239,18 +239,12 @@ def macroop DIV_M
def macroop DIV_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
divr rdx, rax, t1
divq rax, rax, t1
};
'''
#let {{
# class MUL(Inst):
# "GenFault ${new UnimpInstFault}"
# class IMUL(Inst):
# "GenFault ${new UnimpInstFault}"
# class DIV(Inst):
# "GenFault ${new UnimpInstFault}"
# class IDIV(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

12
src/arch/x86/isa/insts/compare_and_test/compare.py
View File

@@ -56,21 +56,21 @@
microcode = '''
def macroop CMP_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t0, reg, t1, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
};
@@ -78,20 +78,20 @@ def macroop CMP_P_I
{
limm t2, imm
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t0, t1, t2, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
};
def macroop CMP_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sub t0, t1, reg, flags=(OF, SF, ZF, AF, PF, CF)
};

64
src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
View File

@@ -64,7 +64,7 @@ def macroop SETZ_M
{
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETZ_P
@@ -72,7 +72,7 @@ def macroop SETZ_P
rdip t7
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNZ_R
@@ -85,7 +85,7 @@ def macroop SETNZ_M
{
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNZ_P
@@ -93,7 +93,7 @@ def macroop SETNZ_P
rdip t7
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETB_R
@@ -106,7 +106,7 @@ def macroop SETB_M
{
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETB_P
@@ -114,7 +114,7 @@ def macroop SETB_P
rdip t7
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNB_R
@@ -127,7 +127,7 @@ def macroop SETNB_M
{
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNB_P
@@ -135,7 +135,7 @@ def macroop SETNB_P
rdip t7
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETBE_R
@@ -148,7 +148,7 @@ def macroop SETBE_M
{
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETBE_P
@@ -156,7 +156,7 @@ def macroop SETBE_P
rdip t7
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNBE_R
@@ -169,7 +169,7 @@ def macroop SETNBE_M
{
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNBE_P
@@ -177,7 +177,7 @@ def macroop SETNBE_P
rdip t7
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETS_R
@@ -190,7 +190,7 @@ def macroop SETS_M
{
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETS_P
@@ -198,7 +198,7 @@ def macroop SETS_P
rdip t7
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNS_R
@@ -211,7 +211,7 @@ def macroop SETNS_M
{
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNS_P
@@ -219,7 +219,7 @@ def macroop SETNS_P
rdip t7
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETP_R
@@ -232,7 +232,7 @@ def macroop SETP_M
{
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETP_P
@@ -240,7 +240,7 @@ def macroop SETP_P
rdip t7
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNP_R
@@ -253,7 +253,7 @@ def macroop SETNP_M
{
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNP_P
@@ -261,7 +261,7 @@ def macroop SETNP_P
rdip t7
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETL_R
@@ -274,7 +274,7 @@ def macroop SETL_M
{
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETL_P
@@ -282,7 +282,7 @@ def macroop SETL_P
rdip t7
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNL_R
@@ -295,7 +295,7 @@ def macroop SETNL_M
{
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNL_P
@@ -303,7 +303,7 @@ def macroop SETNL_P
rdip t7
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETLE_R
@@ -316,7 +316,7 @@ def macroop SETLE_M
{
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETLE_P
@@ -324,7 +324,7 @@ def macroop SETLE_P
rdip t7
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNLE_R
@@ -337,7 +337,7 @@ def macroop SETNLE_M
{
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNLE_P
@@ -345,7 +345,7 @@ def macroop SETNLE_P
rdip t7
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETO_R
@@ -358,7 +358,7 @@ def macroop SETO_M
{
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETO_P
@@ -366,7 +366,7 @@ def macroop SETO_P
rdip t7
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SETNO_R
@@ -379,7 +379,7 @@ def macroop SETNO_M
{
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SETNO_P
@@ -387,6 +387,6 @@ def macroop SETNO_P
rdip t7
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
'''

8
src/arch/x86/isa/insts/compare_and_test/test.py
View File

@@ -56,14 +56,14 @@
microcode = '''
def macroop TEST_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
and t0, t1, reg, flags=(SF, ZF, PF)
};
def macroop TEST_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
and t0, t1, reg, flags=(SF, ZF, PF)
};
@@ -74,7 +74,7 @@ def macroop TEST_R_R
def macroop TEST_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
limm t2, imm
and t0, t1, t2, flags=(SF, ZF, PF)
};
@@ -82,7 +82,7 @@ def macroop TEST_M_I
def macroop TEST_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
limm t2, imm
and t0, t1, t2, flags=(SF, ZF, PF)
};

4
src/arch/x86/isa/insts/control_transfer/call.py
View File

@@ -83,7 +83,7 @@ def macroop CALL_NEAR_M
.adjust_env oszIn64Override
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
subi rsp, rsp, dsz
st t7, ss, [0, t0, rsp]
wripi t1, 0
@@ -95,7 +95,7 @@ def macroop CALL_NEAR_P
.adjust_env oszIn64Override
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
subi rsp, rsp, dsz
st t7, ss, [0, t0, rsp]
wripi t1, 0

166
src/arch/x86/isa/insts/control_transfer/conditional_jump.py
View File

@@ -53,8 +53,164 @@
#
# Authors: Gabe Black
microcode = ""
#let {{
# class JCC(Inst):
# "GenFault ${new UnimpInstFault}"
#}};
microcode = '''
def macroop JZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CZF,)
};
def macroop JNZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCZF,)
};
def macroop JB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCF,)
};
def macroop JNB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCF,)
};
def macroop JBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCvZF,)
};
def macroop JNBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCvZF,)
};
def macroop JS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSF,)
};
def macroop JNS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSF,)
};
def macroop JP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CPF,)
};
def macroop JNP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCPF,)
};
def macroop JL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOF,)
};
def macroop JNL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOF,)
};
def macroop JLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOvZF,)
};
def macroop JNLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOvZF,)
};
def macroop JO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(COF,)
};
def macroop JNO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCOF,)
};
'''

164
src/arch/x86/isa/insts/control_transfer/jump.py
View File

@@ -54,166 +54,6 @@
# Authors: Gabe Black
microcode = '''
def macroop JZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CZF,)
};
def macroop JNZ_I
{
# Make the defualt data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCZF,)
};
def macroop JB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCF,)
};
def macroop JNB_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCF,)
};
def macroop JBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CCvZF,)
};
def macroop JNBE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCCvZF,)
};
def macroop JS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSF,)
};
def macroop JNS_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSF,)
};
def macroop JP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CPF,)
};
def macroop JNP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCPF,)
};
def macroop JL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOF,)
};
def macroop JNL_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOF,)
};
def macroop JLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(CSxOvZF,)
};
def macroop JNLE_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCSxOvZF,)
};
def macroop JO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(COF,)
};
def macroop JNO_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t1
limm t2, imm
wrip t1, t2, flags=(nCOF,)
};
def macroop JMP_I
{
# Make the default data size of jumps 64 bits in 64 bit mode
@@ -237,7 +77,7 @@ def macroop JMP_M
# Make the default data size of jumps 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
wripi t1, 0
};
@@ -247,7 +87,7 @@ def macroop JMP_P
.adjust_env oszIn64Override
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
wripi t1, 0
};
'''

4
src/arch/x86/isa/insts/control_transfer/xreturn.py
View File

@@ -59,7 +59,7 @@ def macroop RET_NEAR
# Make the default data size of rets 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [0, t0, rsp]
ld t1, ss, [1, t0, rsp]
addi rsp, rsp, dsz
wripi t1, 0
};
@@ -70,7 +70,7 @@ def macroop RET_NEAR_I
.adjust_env oszIn64Override
limm t2, imm
ld t1, ss, [0, t0, rsp]
ld t1, ss, [1, t0, rsp]
addi rsp, rsp, dsz
add rsp, rsp, t2
wripi t1, 0

14
src/arch/x86/isa/insts/data_conversion/sign_extension.py
View File

@@ -65,17 +65,3 @@ def macroop CQO_R_R {
sra regm, regm, "env.dataSize * 8 - 1"
};
'''
#let {{
# class CBW(Inst):
# "GenFault ${new UnimpInstFault}"
# class CWDE(Inst):
# "GenFault ${new UnimpInstFault}"
# class CDQE(Inst):
# "GenFault ${new UnimpInstFault}"
# class CWD(Inst):
# "GenFault ${new UnimpInstFault}"
# class CDQ(Inst):
# "GenFault ${new UnimpInstFault}"
# class CQO(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

64
src/arch/x86/isa/insts/data_transfer/conditional_move.py
View File

@@ -61,14 +61,14 @@ def macroop CMOVZ_R_R
def macroop CMOVZ_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVZ_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CZF,)
};
@@ -79,14 +79,14 @@ def macroop CMOVNZ_R_R
def macroop CMOVNZ_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVNZ_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCZF,)
};
@@ -97,14 +97,14 @@ def macroop CMOVB_R_R
def macroop CMOVB_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CCF,)
};
@@ -115,14 +115,14 @@ def macroop CMOVNB_R_R
def macroop CMOVNB_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVNB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCCF,)
};
@@ -133,14 +133,14 @@ def macroop CMOVBE_R_R
def macroop CMOVBE_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVBE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CCvZF,)
};
@@ -151,14 +151,14 @@ def macroop CMOVNBE_R_R
def macroop CMOVNBE_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCCvZF,)
};
@@ -169,14 +169,14 @@ def macroop CMOVS_R_R
def macroop CMOVS_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVS_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CSF,)
};
@@ -187,14 +187,14 @@ def macroop CMOVNS_R_R
def macroop CMOVNS_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVNS_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCSF,)
};
@@ -205,14 +205,14 @@ def macroop CMOVP_R_R
def macroop CMOVP_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVP_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CPF,)
};
@@ -223,14 +223,14 @@ def macroop CMOVNP_R_R
def macroop CMOVNP_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, regm, flags=(nCPF,)
};
@@ -241,14 +241,14 @@ def macroop CMOVL_R_R
def macroop CMOVL_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVL_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CSxOF,)
};
@@ -259,14 +259,14 @@ def macroop CMOVNL_R_R
def macroop CMOVNL_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVNL_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCSxOF,)
};
@@ -277,14 +277,14 @@ def macroop CMOVLE_R_R
def macroop CMOVLE_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(CSxOvZF,)
};
@@ -295,14 +295,14 @@ def macroop CMOVNLE_R_R
def macroop CMOVNLE_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCSxOvZF,)
};
@@ -313,14 +313,14 @@ def macroop CMOVO_R_R
def macroop CMOVO_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVO_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(COF,)
};
@@ -331,14 +331,14 @@ def macroop CMOVNO_R_R
def macroop CMOVNO_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
mov reg, reg, t1, flags=(nCOF,)
};
def macroop CMOVNO_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
mov reg, reg, t1, flags=(nCOF,)
};
'''

38
src/arch/x86/isa/insts/data_transfer/move.py
View File

@@ -64,21 +64,21 @@ def macroop MOV_R_R {
};
def macroop MOV_M_R {
st reg, ds, [scale, index, base], disp
st reg, seg, sib, disp
};
def macroop MOV_P_R {
rdip t7
st reg, ds, [0, t0, t7], disp
st reg, seg, riprel, disp
};
def macroop MOV_R_M {
ld reg, ds, [scale, index, base], disp
ld reg, seg, sib, disp
};
def macroop MOV_R_P {
rdip t7
ld reg, ds, [0, t0, t7], disp
ld reg, seg, riprel, disp
};
def macroop MOV_R_I {
@@ -87,13 +87,13 @@ def macroop MOV_R_I {
def macroop MOV_M_I {
limm t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop MOV_P_I {
rdip t7
limm t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
#
@@ -105,13 +105,13 @@ def macroop MOVSXD_R_R {
};
def macroop MOVSXD_R_M {
ld t1, ds, [scale, index, base], disp, dataSize=4
ld t1, seg, sib, disp, dataSize=4
sext reg, t1, 32
};
def macroop MOVSXD_R_P {
rdip t7
ld t1, ds, [0, t0, t7], disp, dataSize=4
ld t1, seg, riprel, disp, dataSize=4
sext reg, t1, 32
};
@@ -120,13 +120,13 @@ def macroop MOVSX_B_R_R {
};
def macroop MOVSX_B_R_M {
ld reg, ds, [scale, index, base], disp, dataSize=1
ld reg, seg, sib, disp, dataSize=1
sext reg, reg, 8
};
def macroop MOVSX_B_R_P {
rdip t7
ld reg, ds, [0, t0, t7], disp, dataSize=1
ld reg, seg, riprel, disp, dataSize=1
sext reg, reg, 8
};
@@ -135,13 +135,13 @@ def macroop MOVSX_W_R_R {
};
def macroop MOVSX_W_R_M {
ld reg, ds, [scale, index, base], disp, dataSize=2
ld reg, seg, sib, disp, dataSize=2
sext reg, reg, 16
};
def macroop MOVSX_W_R_P {
rdip t7
ld reg, ds, [0, t0, t7], disp, dataSize=2
ld reg, seg, riprel, disp, dataSize=2
sext reg, reg, 16
};
@@ -154,13 +154,13 @@ def macroop MOVZX_B_R_R {
};
def macroop MOVZX_B_R_M {
ld t1, ds, [scale, index, base], disp, dataSize=1
ld t1, seg, sib, disp, dataSize=1
zext reg, t1, 8
};
def macroop MOVZX_B_R_P {
rdip t7
ld t1, ds, [0, t0, t7], disp, dataSize=1
ld t1, seg, riprel, disp, dataSize=1
zext reg, t1, 8
};
@@ -169,23 +169,17 @@ def macroop MOVZX_W_R_R {
};
def macroop MOVZX_W_R_M {
ld t1, ds, [scale, index, base], disp, dataSize=2
ld t1, seg, sib, disp, dataSize=2
zext reg, t1, 16
};
def macroop MOVZX_W_R_P {
rdip t7
ld t1, ds, [0, t0, t7], disp, dataSize=2
ld t1, seg, riprel, disp, dataSize=2
zext reg, t1, 16
};
'''
#let {{
# class MOV(Inst):
# "Mov ^0 ^0 ^1"
# class MOVSX(Inst):
# "GenFault ${new UnimpInstFault}"
# class MOVZX(Inst):
# "GenFault ${new UnimpInstFault}"
# class MOVD(Inst):
# "GenFault ${new UnimpInstFault}"
# class MOVNTI(Inst):

56
src/arch/x86/isa/insts/data_transfer/stack_operations.py
View File

@@ -58,7 +58,7 @@ def macroop POP_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld reg, ss, [0, t0, rsp]
ld reg, ss, [1, t0, rsp]
addi rsp, rsp, dsz
};
@@ -66,9 +66,9 @@ def macroop POP_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [0, t0, rsp]
ld t1, ss, [1, t0, rsp]
addi rsp, rsp, dsz
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop POP_P {
@@ -76,9 +76,9 @@ def macroop POP_P {
.adjust_env oszIn64Override
rdip t7
ld t1, ss, [0, t0, rsp]
ld t1, ss, [1, t0, rsp]
addi rsp, rsp, dsz
st t1, ds, [0, t0, t7]
st t1, seg, riprel, disp
};
def macroop PUSH_R {
@@ -87,7 +87,7 @@ def macroop PUSH_R {
# This needs to work slightly differently from the other versions of push
# because the -original- version of the stack pointer is what gets pushed
st reg, ss, [0, t0, rsp], "-env.dataSize"
st reg, ss, [1, t0, rsp], "-env.dataSize"
subi rsp, rsp, dsz
};
@@ -97,16 +97,16 @@ def macroop PUSH_I {
limm t1, imm
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
st t1, ss, [1, t0, rsp]
};
def macroop PUSH_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
st t1, ss, [1, t0, rsp]
};
def macroop PUSH_P {
@@ -114,31 +114,31 @@ def macroop PUSH_P {
.adjust_env oszIn64Override
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
st t1, ss, [1, t0, rsp]
};
def macroop PUSHA {
st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
st rax, ss, [1, t0, rsp], "-0 * env.dataSize"
st rcx, ss, [1, t0, rsp], "-1 * env.dataSize"
st rdx, ss, [1, t0, rsp], "-2 * env.dataSize"
st rbx, ss, [1, t0, rsp], "-3 * env.dataSize"
st rsp, ss, [1, t0, rsp], "-4 * env.dataSize"
st rbp, ss, [1, t0, rsp], "-5 * env.dataSize"
st rsi, ss, [1, t0, rsp], "-6 * env.dataSize"
st rdi, ss, [1, t0, rsp], "-7 * env.dataSize"
subi rsp, rsp, "8 * env.dataSize"
};
def macroop POPA {
ld rdi, ss, [0, t0, rsp], "0 * env.dataSize"
ld rsi, ss, [0, t0, rsp], "1 * env.dataSize"
ld rbp, ss, [0, t0, rsp], "2 * env.dataSize"
ld rbx, ss, [0, t0, rsp], "4 * env.dataSize"
ld rdx, ss, [0, t0, rsp], "5 * env.dataSize"
ld rcx, ss, [0, t0, rsp], "6 * env.dataSize"
ld rax, ss, [0, t0, rsp], "7 * env.dataSize"
ld rdi, ss, [1, t0, rsp], "0 * env.dataSize"
ld rsi, ss, [1, t0, rsp], "1 * env.dataSize"
ld rbp, ss, [1, t0, rsp], "2 * env.dataSize"
ld rbx, ss, [1, t0, rsp], "4 * env.dataSize"
ld rdx, ss, [1, t0, rsp], "5 * env.dataSize"
ld rcx, ss, [1, t0, rsp], "6 * env.dataSize"
ld rax, ss, [1, t0, rsp], "7 * env.dataSize"
addi rsp, rsp, "8 * env.dataSize"
};
@@ -147,13 +147,11 @@ def macroop LEAVE {
.adjust_env oszIn64Override
mov rsp, rsp, rbp
ld rbp, ss, [0, t0, rsp]
ld rbp, ss, [1, t0, rsp]
addi rsp, rsp, dsz
};
'''
#let {{
# class ENTER(Inst):
# "GenFault ${new UnimpInstFault}"
# class LEAVE(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

16
src/arch/x86/isa/insts/data_transfer/xchg.py
View File

@@ -68,31 +68,31 @@ def macroop XCHG_R_R
def macroop XCHG_R_M
{
ld t1, ds, [scale, index, base], disp
st reg, ds, [scale, index, base], disp
ld t1, seg, sib, disp
st reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
st reg, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
st reg, seg, riprel, disp
mov reg, reg, t1
};
def macroop XCHG_M_R
{
ld t1, ds, [scale, index, base], disp
st reg, ds, [scale, index, base], disp
ld t1, seg, sib, disp
st reg, seg, sib, disp
mov reg, reg, t1
};
def macroop XCHG_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
st reg, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
st reg, seg, riprel, disp
mov reg, reg, t1
};
'''

4
src/arch/x86/isa/insts/load_effective_address.py
View File

@@ -55,11 +55,11 @@
microcode = '''
def macroop LEA_R_M {
lea reg, ds, [scale, index, base], disp
lea reg, seg, sib, disp
};
def macroop LEA_R_P {
rdip t7
lea reg, ds, [0, t0, t7], disp
lea reg, seg, riprel, disp
};
'''

68
src/arch/x86/isa/insts/logical.py
View File

@@ -62,45 +62,45 @@ def macroop OR_R_R
def macroop OR_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop OR_P_I
{
limm t2, imm
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
or t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop OR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop OR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
or t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop OR_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
def macroop OR_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
or reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
@@ -124,45 +124,45 @@ def macroop XOR_R_I
def macroop XOR_M_I
{
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop XOR_P_I
{
limm t2, imm
rdip t7
ld t1, ds, [1, t0, t7], disp
ld t1, seg, riprel, disp
xor t1, t1, t2, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [1, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop XOR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop XOR_P_R
{
rdip t7
ld t1, ds, [1, t0, t7], disp
ld t1, seg, riprel, disp
xor t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, riprel, disp
};
def macroop XOR_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
def macroop XOR_R_P
{
rdip t7
ld t1, ds, [1, t0, t7], disp
ld t1, seg, riprel, disp
xor reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
@@ -173,14 +173,14 @@ def macroop AND_R_R
def macroop AND_R_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
def macroop AND_R_P
{
rdip t7
ld t1, ds, [1, t0, t7], disp
ld t1, seg, riprel, disp
and reg, reg, t1, flags=(OF,SF,ZF,PF,CF)
};
@@ -192,34 +192,34 @@ def macroop AND_R_I
def macroop AND_M_I
{
ld t2, ds, [scale, index, base], disp
ld t2, seg, sib, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
st t2, ds, [scale, index, base], disp
st t2, seg, sib, disp
};
def macroop AND_P_I
{
rdip t7
ld t2, ds, [0, t0, t7], disp
ld t2, seg, riprel, disp
limm t1, imm
and t2, t2, t1, flags=(OF,SF,ZF,PF,CF)
st t2, ds, [0, t0, t7], disp
st t2, seg, riprel, disp
};
def macroop AND_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop AND_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
and t1, t1, reg, flags=(OF,SF,ZF,PF,CF)
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop NOT_R
@@ -231,17 +231,17 @@ def macroop NOT_R
def macroop NOT_M
{
limm t1, -1
ld t2, ds, [scale, index, base], disp
ld t2, seg, sib, disp
xor t2, t2, t1
st t2, ds, [scale, index, base], disp
st t2, seg, sib, disp
};
def macroop NOT_P
{
limm t1, -1
rdip t7
ld t2, ds, [0, t0, t7], disp
ld t2, seg, riprel, disp
xor t2, t2, t1
st t2, ds, [0, t0, t7], disp
st t2, seg, riprel, disp
};
'''

4
src/arch/x86/isa/insts/processor_information.py
View File

@@ -67,7 +67,3 @@ def macroop CPUID_R {
limm rcx, 0x444d4163, dataSize=4
};
'''
#let {{
# class CPUID(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

96
src/arch/x86/isa/insts/rotate_and_shift/rotate.py
View File

@@ -61,17 +61,17 @@ def macroop ROL_R_I
def macroop ROL_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
roli t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
roli t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ROL_1_R
@@ -81,17 +81,17 @@ def macroop ROL_1_R
def macroop ROL_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
roli t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
roli t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ROL_R_R
@@ -101,17 +101,17 @@ def macroop ROL_R_R
def macroop ROL_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rol t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rol t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ROR_R_I
@@ -121,17 +121,17 @@ def macroop ROR_R_I
def macroop ROR_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rori t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rori t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ROR_1_R
@@ -141,17 +141,17 @@ def macroop ROR_1_R
def macroop ROR_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rori t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rori t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop ROR_R_R
@@ -161,17 +161,17 @@ def macroop ROR_R_R
def macroop ROR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
ror t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop ROR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
ror t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCL_R_I
@@ -181,17 +181,17 @@ def macroop RCL_R_I
def macroop RCL_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcli t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcli t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCL_1_R
@@ -201,17 +201,17 @@ def macroop RCL_1_R
def macroop RCL_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcli t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcli t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCL_R_R
@@ -221,17 +221,17 @@ def macroop RCL_R_R
def macroop RCL_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcl t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcl t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCR_R_I
@@ -241,17 +241,17 @@ def macroop RCR_R_I
def macroop RCR_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcri t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcri t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCR_1_R
@@ -261,17 +261,17 @@ def macroop RCR_1_R
def macroop RCR_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcri t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcri t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop RCR_R_R
@@ -281,16 +281,16 @@ def macroop RCR_R_R
def macroop RCR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
rcr t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop RCR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
rcr t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
'''

72
src/arch/x86/isa/insts/rotate_and_shift/shift.py
View File

@@ -61,17 +61,17 @@ def macroop SAL_R_I
def macroop SAL_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
slli t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
slli t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SAL_1_R
@@ -81,17 +81,17 @@ def macroop SAL_1_R
def macroop SAL_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
slli t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
slli t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SAL_R_R
@@ -101,17 +101,17 @@ def macroop SAL_R_R
def macroop SAL_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sll t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sll t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SHR_R_I
@@ -121,17 +121,17 @@ def macroop SHR_R_I
def macroop SHR_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
srli t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SHR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
srli t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SHR_1_R
@@ -141,17 +141,17 @@ def macroop SHR_1_R
def macroop SHR_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
srli t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SHR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
srli t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SHR_R_R
@@ -161,17 +161,17 @@ def macroop SHR_R_R
def macroop SHR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
srl t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SHR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
srl t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SAR_R_I
@@ -181,17 +181,17 @@ def macroop SAR_R_I
def macroop SAR_M_I
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
srai t1, t1, imm
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
srai t1, t1, imm
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SAR_1_R
@@ -201,17 +201,17 @@ def macroop SAR_1_R
def macroop SAR_1_M
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
srai t1, t1, 1
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
srai t1, t1, 1
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
def macroop SAR_R_R
@@ -221,16 +221,16 @@ def macroop SAR_R_R
def macroop SAR_M_R
{
ld t1, ds, [scale, index, base], disp
ld t1, seg, sib, disp
sra t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, seg, sib, disp
};
def macroop SAR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ld t1, seg, riprel, disp
sra t1, t1, reg
st t1, ds, [0, t0, t7], disp
st t1, seg, riprel, disp
};
'''

1
src/arch/x86/isa/macroop.isa
View File

@@ -196,6 +196,7 @@ let {{
self.regUsed = False
self.regm = "0"
self.regmUsed = False
self.seg = "SEGMENT_REG_DS"
self.size = None
self.addressSize = "ADDRSIZE"
self.dataSize = "OPSIZE"

9
src/arch/x86/isa/microasm.isa
View File

@@ -84,6 +84,7 @@ let {{
"regm" : "env.regm",
"imm" : "IMMEDIATE",
"disp" : "DISPLACEMENT",
"seg" : "env.seg",
"scale" : "env.scale",
"index" : "env.index",
"base" : "env.base",
@@ -91,10 +92,16 @@ let {{
"osz" : "env.operandSize",
"ssz" : "env.stackSize"
}
assembler.symbols.update(symbols)
# Short hand for common scale-index-base combinations.
assembler.symbols["sib"] = \
[symbols["scale"], symbols["index"], symbols["base"]]
assembler.symbols["riprel"] = \
["1", assembler.symbols["t0"], assembler.symbols["t7"]]
for reg in ('ax', 'bx', 'cx', 'dx', 'sp', 'bp', 'si', 'di'):
assembler.symbols["r%s" % reg] = "INTREG_R%s" % reg.upper()
assembler.symbols.update(symbols)
for flag in ('CF', 'PF', 'ECF', 'AF', 'EZF', 'ZF', 'SF', 'OF'):
assembler.symbols[flag] = flag + "Bit"

2
src/arch/x86/isa/microops/ldstop.isa
View File

@@ -362,7 +362,7 @@ let {{
decoder_output = ""
exec_output = ""
calculateEA = "EA = scale * Index + Base + disp;"
calculateEA = "EA = SegBase + scale * Index + Base + disp;"
def defineMicroLoadOp(mnemonic, code):
global header_output

1
src/arch/x86/isa/operands.isa
View File

@@ -105,5 +105,6 @@ def operands {{
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
'SegBase': ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
}};

2
src/arch/x86/miscregfile.cc
View File

@@ -127,7 +127,6 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
{
warn("No miscreg effects implemented yet!\n");
return readRegNoEffect(miscReg);
}
@@ -155,7 +154,6 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
void MiscRegFile::setReg(int miscReg,
const MiscReg &val, ThreadContext * tc)
{
warn("No miscreg effects implemented yet!\n");
setRegNoEffect(miscReg, val);
}

10
src/arch/x86/process.cc
View File

@@ -88,6 +88,7 @@
#include "arch/x86/isa_traits.hh"
#include "arch/x86/process.hh"
#include "arch/x86/segmentregs.hh"
#include "arch/x86/types.hh"
#include "base/loader/object_file.hh"
#include "base/loader/elf_object.hh"
@@ -145,13 +146,8 @@ void
X86LiveProcess::startup()
{
argsInit(sizeof(IntReg), VMPageSize);
//The AMD64 abi says that only rsp and rdx are defined at process
//startup. rsp will be set by argsInit, and I don't understand what
//rdx should be set to. The other floating point and integer registers
//will be zeroed by the register file constructors, but control registers
//should be initialized here. Since none of those are implemented, there
//isn't anything here.
for(int i = 0; i < NUM_SEGMENTREGS; i++)
threadContexts[0]->setMiscRegNoEffect(MISCREG_ES_BASE + i, 0);
}
void

6
src/arch/x86/types.hh
View File

@@ -71,12 +71,12 @@ namespace X86ISA
enum Prefixes {
NoOverride,
CSOverride,
DSOverride,
ESOverride,
CSOverride,
SSOverride,
DSOverride,
FSOverride,
GSOverride,
SSOverride,
RexPrefix,
OperandSizeOverride,
AddressSizeOverride,