configs: Use devices.SimpleSeSystem in starter_se.py
Change-Id: I742e280e7a2a4047ac4bb3d783a28ee97f461480 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Richard Cooper <richard.cooper@arm.com>
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@@ -64,72 +64,6 @@ cpu_types = {
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}
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class SimpleSeSystem(System):
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"""
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Example system class for syscall emulation mode
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"""
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# Use a fixed cache line size of 64 bytes
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cache_line_size = 64
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def __init__(self, args, **kwargs):
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super(SimpleSeSystem, self).__init__(**kwargs)
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# Setup book keeping to be able to use CpuClusters from the
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# devices module.
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self._clusters = []
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self._num_cpus = 0
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# Create a voltage and clock domain for system components
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self.voltage_domain = VoltageDomain(voltage="3.3V")
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self.clk_domain = SrcClockDomain(
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clock="1GHz", voltage_domain=self.voltage_domain
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)
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# Create the off-chip memory bus.
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self.membus = SystemXBar()
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# Wire up the system port that gem5 uses to load the kernel
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# and to perform debug accesses.
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self.system_port = self.membus.cpu_side_ports
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# Add CPUs to the system. A cluster of CPUs typically have
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# private L1 caches and a shared L2 cache.
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self.cpu_cluster = devices.ArmCpuCluster(
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self,
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args.num_cores,
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args.cpu_freq,
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"1.2V",
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*cpu_types[args.cpu],
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tarmac_gen=args.tarmac_gen,
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tarmac_dest=args.tarmac_dest,
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)
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# Create a cache hierarchy (unless we are simulating a
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# functional CPU in atomic memory mode) for the CPU cluster
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# and connect it to the shared memory bus.
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if self.cpu_cluster.memory_mode() == "timing":
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self.cpu_cluster.addL1()
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self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
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self.cpu_cluster.connectMemSide(self.membus)
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# Tell gem5 about the memory mode used by the CPUs we are
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# simulating.
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self.mem_mode = self.cpu_cluster.memory_mode()
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def numCpuClusters(self):
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return len(self._clusters)
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def addCpuCluster(self, cpu_cluster):
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assert cpu_cluster not in self._clusters
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assert len(cpu_cluster) > 0
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self._clusters.append(cpu_cluster)
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self._num_cpus += len(cpu_cluster)
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def numCpus(self):
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return self._num_cpus
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def get_processes(cmd):
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"""Interprets commands to run and returns a list of processes"""
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@@ -150,7 +84,31 @@ def get_processes(cmd):
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def create(args):
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"""Create and configure the system object."""
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system = SimpleSeSystem(args)
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cpu_class = cpu_types[args.cpu][0]
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mem_mode = cpu_class.memory_mode()
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# Only simulate caches when using a timing CPU (e.g., the HPI model)
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want_caches = True if mem_mode == "timing" else False
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system = devices.SimpleSeSystem(
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mem_mode=mem_mode,
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)
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# Add CPUs to the system. A cluster of CPUs typically have
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# private L1 caches and a shared L2 cache.
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system.cpu_cluster = devices.ArmCpuCluster(
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system,
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args.num_cores,
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args.cpu_freq,
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"1.2V",
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*cpu_types[args.cpu],
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tarmac_gen=args.tarmac_gen,
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tarmac_dest=args.tarmac_dest,
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)
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# Create a cache hierarchy for the cluster. We are assuming that
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# clusters have core-private L1 caches and an L2 that's shared
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# within the cluster.
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system.addCaches(want_caches, last_cache_level=2)
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# Tell components about the expected physical memory ranges. This
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# is, for example, used by the MemConfig helper to determine where
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@@ -160,6 +118,9 @@ def create(args):
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# Configure the off-chip memory system.
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MemConfig.config_mem(args, system)
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# Wire up the system's memory system
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system.connect()
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# Parse the command line and get a list of Processes instances
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# that we can pass to gem5.
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processes = get_processes(args.commands_to_run)
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