diff --git a/configs/example/arm/starter_se.py b/configs/example/arm/starter_se.py
index f21f399675..9834487155 100644
--- a/configs/example/arm/starter_se.py
+++ b/configs/example/arm/starter_se.py
@@ -64,72 +64,6 @@ cpu_types = {
 }
 
 
-class SimpleSeSystem(System):
-    """
-    Example system class for syscall emulation mode
-    """
-
-    # Use a fixed cache line size of 64 bytes
-    cache_line_size = 64
-
-    def __init__(self, args, **kwargs):
-        super(SimpleSeSystem, self).__init__(**kwargs)
-
-        # Setup book keeping to be able to use CpuClusters from the
-        # devices module.
-        self._clusters = []
-        self._num_cpus = 0
-
-        # Create a voltage and clock domain for system components
-        self.voltage_domain = VoltageDomain(voltage="3.3V")
-        self.clk_domain = SrcClockDomain(
-            clock="1GHz", voltage_domain=self.voltage_domain
-        )
-
-        # Create the off-chip memory bus.
-        self.membus = SystemXBar()
-
-        # Wire up the system port that gem5 uses to load the kernel
-        # and to perform debug accesses.
-        self.system_port = self.membus.cpu_side_ports
-
-        # Add CPUs to the system. A cluster of CPUs typically have
-        # private L1 caches and a shared L2 cache.
-        self.cpu_cluster = devices.ArmCpuCluster(
-            self,
-            args.num_cores,
-            args.cpu_freq,
-            "1.2V",
-            *cpu_types[args.cpu],
-            tarmac_gen=args.tarmac_gen,
-            tarmac_dest=args.tarmac_dest,
-        )
-
-        # Create a cache hierarchy (unless we are simulating a
-        # functional CPU in atomic memory mode) for the CPU cluster
-        # and connect it to the shared memory bus.
-        if self.cpu_cluster.memory_mode() == "timing":
-            self.cpu_cluster.addL1()
-            self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
-        self.cpu_cluster.connectMemSide(self.membus)
-
-        # Tell gem5 about the memory mode used by the CPUs we are
-        # simulating.
-        self.mem_mode = self.cpu_cluster.memory_mode()
-
-    def numCpuClusters(self):
-        return len(self._clusters)
-
-    def addCpuCluster(self, cpu_cluster):
-        assert cpu_cluster not in self._clusters
-        assert len(cpu_cluster) > 0
-        self._clusters.append(cpu_cluster)
-        self._num_cpus += len(cpu_cluster)
-
-    def numCpus(self):
-        return self._num_cpus
-
-
 def get_processes(cmd):
     """Interprets commands to run and returns a list of processes"""
 
@@ -150,7 +84,31 @@ def get_processes(cmd):
 def create(args):
     """Create and configure the system object."""
 
-    system = SimpleSeSystem(args)
+    cpu_class = cpu_types[args.cpu][0]
+    mem_mode = cpu_class.memory_mode()
+    # Only simulate caches when using a timing CPU (e.g., the HPI model)
+    want_caches = True if mem_mode == "timing" else False
+
+    system = devices.SimpleSeSystem(
+        mem_mode=mem_mode,
+    )
+
+    # Add CPUs to the system. A cluster of CPUs typically have
+    # private L1 caches and a shared L2 cache.
+    system.cpu_cluster = devices.ArmCpuCluster(
+        system,
+        args.num_cores,
+        args.cpu_freq,
+        "1.2V",
+        *cpu_types[args.cpu],
+        tarmac_gen=args.tarmac_gen,
+        tarmac_dest=args.tarmac_dest,
+    )
+
+    # Create a cache hierarchy for the cluster. We are assuming that
+    # clusters have core-private L1 caches and an L2 that's shared
+    # within the cluster.
+    system.addCaches(want_caches, last_cache_level=2)
 
     # Tell components about the expected physical memory ranges. This
     # is, for example, used by the MemConfig helper to determine where
@@ -160,6 +118,9 @@ def create(args):
     # Configure the off-chip memory system.
     MemConfig.config_mem(args, system)
 
+    # Wire up the system's memory system
+    system.connect()
+
     # Parse the command line and get a list of Processes instances
     # that we can pass to gem5.
     processes = get_processes(args.commands_to_run)