ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.

2009-11-14 19:22:30 -08:00
parent 425ebf6bd7
commit e2ab64543b
1 changed files with 4 additions and 0 deletions
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -93,6 +93,10 @@ namespace ArmISA
        Bitfield<4, 0> mode;
    EndBitUnion(CPSR)

+    // This mask selects bits of the CPSR that actually go in the CondCodes
+    // integer register to allow renaming.
+    static const uint32_t CondCodesMask = 0xF80F0000;
+
    BitUnion32(SCTLR)
        Bitfield<30> te;  // Thumb Exception Enable
        Bitfield<29> afe; // Access flag enable