mem: Address mapping with fine-grained channel interleaving
This patch adds an address mapping scheme where the channel interleaving takes place on a cache line granularity. It is similar to the existing RaBaChCo that interleaves on a DRAM page, but should give higher performance when there is less locality in the address stream.
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@@ -44,11 +44,11 @@ from AbstractMemory import *
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class MemSched(Enum): vals = ['fcfs', 'frfcfs']
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# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank,
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# column, bank and channel, respectively, and going from MSB to LSB,
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# the two schemes available are RaBaChCo and CoRaBaCh, either
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# optimising for sequential accesses hitting in the open row, or
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# maximising parallelism.
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class AddrMap(Enum): vals = ['RaBaChCo', 'CoRaBaCh']
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# column, bank and channel, respectively, and going from MSB to LSB.
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# Available are RaBaChCo and RaBaCoCh, that are suitable for an
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# open-page policy, optimising for sequential accesses hitting in the
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# open row. For a closed-page policy, CoRaBaCh maximises parallelism.
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class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh']
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# Enum for the page policy, either open or close.
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class PageManage(Enum): vals = ['open', 'close']
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@@ -118,6 +118,11 @@ SimpleDRAM::init()
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panic("Interleaving of %s doesn't match RaBaChCo address map\n",
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name());
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}
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} else if (addrMapping == Enums::RaBaCoCh) {
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if (bytesPerCacheLine != range.granularity()) {
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panic("Interleaving of %s doesn't match RaBaCoCh address map\n",
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name());
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}
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} else if (addrMapping == Enums::CoRaBaCh) {
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if (bytesPerCacheLine != range.granularity())
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panic("Interleaving of %s doesn't match CoRaBaCh address map\n",
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@@ -173,11 +178,9 @@ SimpleDRAM::writeQueueFull() const
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SimpleDRAM::DRAMPacket*
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SimpleDRAM::decodeAddr(PacketPtr pkt)
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{
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// decode the address based on the address mapping scheme
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//
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// with Ra, Co, Ba and Ch denoting rank, column, bank and channel,
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// respectively, and going from MSB to LSB, the two schemes are
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// RaBaChCo and CoRaBaCh
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// decode the address based on the address mapping scheme, with
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// Ra, Co, Ba and Ch denoting rank, column, bank and channel,
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// respectively
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uint8_t rank;
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uint16_t bank;
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uint16_t row;
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@@ -188,20 +191,36 @@ SimpleDRAM::decodeAddr(PacketPtr pkt)
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addr = addr / bytesPerCacheLine;
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// we have removed the lowest order address bits that denote the
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// position within the cache line, proceed and select the
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// appropriate bits for bank, rank and row (no column address is
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// needed)
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// position within the cache line
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if (addrMapping == Enums::RaBaChCo) {
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// the lowest order bits denote the column to ensure that
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// sequential cache lines occupy the same row
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addr = addr / linesPerRowBuffer;
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// take out the channel part of the address, note that this has
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// to match with how accesses are interleaved between the
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// controllers in the address mapping
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// take out the channel part of the address
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addr = addr / channels;
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// after the channel bits, we get the bank bits to interleave
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// after the channel bits, get the bank bits to interleave
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// over the banks
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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// after the bank, we get the rank bits which thus interleaves
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// over the ranks
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rank = addr % ranksPerChannel;
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addr = addr / ranksPerChannel;
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// lastly, get the row bits
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row = addr % rowsPerBank;
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addr = addr / rowsPerBank;
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} else if (addrMapping == Enums::RaBaCoCh) {
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// take out the channel part of the address
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addr = addr / channels;
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// next, the column
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addr = addr / linesPerRowBuffer;
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// after the column bits, we get the bank bits to interleave
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// over the banks
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bank = addr % banksPerRank;
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addr = addr / banksPerRank;
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@@ -474,7 +493,7 @@ SimpleDRAM::printParams() const
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string scheduler = memSchedPolicy == Enums::fcfs ? "FCFS" : "FR-FCFS";
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string address_mapping = addrMapping == Enums::RaBaChCo ? "RaBaChCo" :
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"CoRaBaCh";
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(addrMapping == Enums::RaBaCoCh ? "RaBaCoCh" : "CoRaBaCh");
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string page_policy = pageMgmt == Enums::open ? "OPEN" : "CLOSE";
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DPRINTF(DRAM,
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