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configs, dev, learning-gem5, python, tests: more clarification

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This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
This commit is contained in:
Erin Le
2024-08-24 01:01:04 +00:00
committed by Erin (Jianghua) Le
parent 28453a0e3e
commit e1db67c4bd
87 changed files with 255 additions and 249 deletions
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4
tests/gem5/checkpoint_tests/configs/arm-hello-restore-checkpoint.py
View File

@@ -52,10 +52,10 @@ from gem5.utils.requires import requires
requires(isa_required=ISA.ARM)
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
)
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)

4
tests/gem5/checkpoint_tests/configs/arm-hello-save-checkpoint.py
View File

@@ -52,10 +52,10 @@ args = parser.parse_args()
requires(isa_required=ISA.ARM)
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB", l1i_size="16kB", l2_size="256kB"
l1d_size="16KiB", l1i_size="16KiB", l2_size="256KiB"
)
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.ARM, num_cores=2)
board = SimpleBoard(
clk_freq="3GHz",

2
tests/gem5/checkpoint_tests/configs/power-hello-restore-checkpoint.py
View File

@@ -50,7 +50,7 @@ requires(isa_required=ISA.POWER)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/power-hello-save-checkpoint.py
View File

@@ -58,7 +58,7 @@ requires(isa_required=ISA.POWER)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.POWER, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/sparc-hello-restore-checkpoint.py
View File

@@ -50,7 +50,7 @@ requires(isa_required=ISA.SPARC)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
)

2
tests/gem5/checkpoint_tests/configs/sparc-hello-save-checkpoint.py
View File

@@ -58,7 +58,7 @@ requires(isa_required=ISA.SPARC)
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING, isa=ISA.SPARC, num_cores=2
)

4
tests/gem5/checkpoint_tests/configs/x86-hello-restore-checkpoint.py
View File

@@ -50,9 +50,9 @@ from gem5.utils.requires import requires
requires(isa_required=ISA.X86)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16KiB", l1i_size="16KiB")
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
board = SimpleBoard(
clk_freq="3GHz",

4
tests/gem5/checkpoint_tests/configs/x86-hello-save-checkpoint.py
View File

@@ -58,9 +58,9 @@ parser.add_argument(
args = parser.parse_args()
requires(isa_required=ISA.X86)
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16kB", l1i_size="16kB")
cache_hierarchy = PrivateL1CacheHierarchy(l1d_size="16KiB", l1i_size="16KiB")
memory = SingleChannelDDR3_1600(size="32MB")
memory = SingleChannelDDR3_1600(size="32MiB")
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, isa=ISA.X86, num_cores=4)
board = SimpleBoard(

2
tests/gem5/fs/linux/arm/configs/arm_generic.py
View File

@@ -91,7 +91,7 @@ class LinuxArmSystemBuilder:
self.aarch64_kernel = aarch64_kernel
self.enable_dvm = enable_dvm
self.num_cpus = kwargs.get("num_cpus", 1)
self.mem_size = kwargs.get("mem_size", "256MB")
self.mem_size = kwargs.get("mem_size", "256MiB")
self.use_ruby = kwargs.get("use_ruby", False)
def init_kvm(self, system):

6
tests/gem5/m5threads_test_atomic/caches.py
View File

@@ -77,7 +77,7 @@ class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the size
size = "32kB"
size = "32KiB"
def __init__(self, opts=None):
super().__init__(opts)
@@ -91,7 +91,7 @@ class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the size
size = "32kB"
size = "32KiB"
def __init__(self, opts=None):
super().__init__(opts)
@@ -105,7 +105,7 @@ class L2Cache(PrefetchCache):
"""Simple L2 Cache with default values"""
# Default parameters
size = "256kB"
size = "256KiB"
assoc = 16
tag_latency = 10
data_latency = 10