configs, dev, learning-gem5, python, tests: more clarification

This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631

configs/learning_gem5/part1/caches.py

@@ -71,7 +71,7 @@ class L1ICache(L1Cache):
     """Simple L1 instruction cache with default values"""
 
     # Set the default size
-    size = "16kB"
+    size = "16KiB"
 
     SimpleOpts.add_option(
         "--l1i_size", help=f"L1 instruction cache size. Default: {size}"
@@ -92,7 +92,7 @@ class L1DCache(L1Cache):
     """Simple L1 data cache with default values"""
 
     # Set the default size
-    size = "64kB"
+    size = "64KiB"
 
     SimpleOpts.add_option(
         "--l1d_size", help=f"L1 data cache size. Default: {size}"
@@ -113,7 +113,7 @@ class L2Cache(Cache):
     """Simple L2 Cache with default values"""
 
     # Default parameters
-    size = "256kB"
+    size = "256KiB"
     assoc = 8
     tag_latency = 20
     data_latency = 20

configs/learning_gem5/part1/simple-arm.py

@@ -39,7 +39,7 @@ system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 system.mem_mode = "timing"
-system.mem_ranges = [AddrRange("512MB")]
+system.mem_ranges = [AddrRange("512MiB")]
 system.cpu = ArmTimingSimpleCPU()
 
 system.membus = SystemXBar()

configs/learning_gem5/part1/simple-riscv.py

@@ -39,7 +39,7 @@ system.clk_domain.clock = "1GHz"
 system.clk_domain.voltage_domain = VoltageDomain()
 
 system.mem_mode = "timing"
-system.mem_ranges = [AddrRange("512MB")]
+system.mem_ranges = [AddrRange("512MiB")]
 system.cpu = RiscvTimingSimpleCPU()
 
 system.membus = SystemXBar()

configs/learning_gem5/part1/simple.py

@@ -54,7 +54,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create a simple CPU
 # You can use ISA-specific CPU models for different workloads:

configs/learning_gem5/part1/two_level.py

@@ -77,7 +77,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = X86TimingSimpleCPU()

configs/learning_gem5/part2/simple_cache.py

@@ -46,7 +46,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = X86TimingSimpleCPU()
@@ -55,7 +55,7 @@ system.cpu = X86TimingSimpleCPU()
 system.membus = SystemXBar()
 
 # Create a simple cache
-system.cache = SimpleCache(size="1kB")
+system.cache = SimpleCache(size="1KiB")
 
 # Connect the I and D cache ports of the CPU to the memobj.
 # Since cpu_side is a vector port, each time one of these is connected, it will

configs/learning_gem5/part2/simple_memobj.py

@@ -46,7 +46,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create a simple CPU
 system.cpu = X86TimingSimpleCPU()

configs/learning_gem5/part3/msi_caches.py

@@ -127,7 +127,9 @@ class L1Cache(L1Cache_Controller):
         self.version = self.versionCount()
         # This is the cache memory object that stores the cache data and tags
         self.cacheMemory = RubyCache(
-            size="16kB", assoc=8, start_index_bit=self.getBlockSizeBits(system)
+            size="16KiB",
+            assoc=8,
+            start_index_bit=self.getBlockSizeBits(system),
         )
         self.clk_domain = cpu.clk_domain
         self.send_evictions = self.sendEvicts(cpu)

configs/learning_gem5/part3/ruby_caches_MI_example.py

@@ -125,7 +125,9 @@ class L1Cache(L1Cache_Controller):
         self.version = self.versionCount()
         # This is the cache memory object that stores the cache data and tags
         self.cacheMemory = RubyCache(
-            size="16kB", assoc=8, start_index_bit=self.getBlockSizeBits(system)
+            size="16KiB",
+            assoc=8,
+            start_index_bit=self.getBlockSizeBits(system),
         )
         self.clk_domain = cpu.clk_domain
         self.send_evictions = self.sendEvicts(cpu)

configs/learning_gem5/part3/ruby_test.py

@@ -51,7 +51,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create the tester
 system.tester = RubyTester(
@@ -59,7 +59,7 @@ system.tester = RubyTester(
 )
 
 # Create a simple memory controller and connect it to the membus
-system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s")
+system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GiB/s")
 system.mem_ctrl.range = system.mem_ranges[0]
 
 # Create the Ruby System

configs/learning_gem5/part3/simple_ruby.py

@@ -60,7 +60,7 @@ system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set up the system
 system.mem_mode = "timing"  # Use timing accesses
-system.mem_ranges = [AddrRange("512MB")]  # Create an address range
+system.mem_ranges = [AddrRange("512MiB")]  # Create an address range
 
 # Create a pair of simple CPUs
 system.cpu = [X86TimingSimpleCPU() for i in range(2)]