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configs, dev, learning-gem5, python, tests: more clarification

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This commit contains the rest of the base 2 vs base 10 cache/memory
size clarifications. It also changes the warning message to use
warn(). With these changes, the warning message should now no
longer show up during a fresh compilation of gem5.

Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
This commit is contained in:
Erin Le
2024-08-24 01:01:04 +00:00
committed by Erin (Jianghua) Le
parent 28453a0e3e
commit e1db67c4bd
87 changed files with 255 additions and 249 deletions
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10
configs/dram/lat_mem_rd.py
View File

@@ -98,7 +98,7 @@ parser.add_argument(
"--mem-size",
action="store",
type=str,
default="16MB",
default="16MiB",
help="Specify the memory size",
)
parser.add_argument(
@@ -161,7 +161,7 @@ def is_pow2(num):
# assume we start every range at 0
max_range = int(mem_range.end)
# start at a size of 4 kByte, and go up till we hit the max, increase
# start at a size of 4 kibibyte, and go up till we hit the max, increase
# the step every time we hit a power of two
min_range = 4096
ranges = [min_range]
@@ -295,17 +295,17 @@ class L3Cache(Cache):
# note that everything is in the same clock domain, 2.0 GHz as
# specified above
system.l1cache = L1_DCache(size="64kB")
system.l1cache = L1_DCache(size="64KiB")
system.monitor.mem_side_port = system.l1cache.cpu_side
system.l2cache = L2Cache(size="512kB", writeback_clean=True)
system.l2cache = L2Cache(size="512KiB", writeback_clean=True)
system.l2cache.xbar = L2XBar()
system.l1cache.mem_side = system.l2cache.xbar.cpu_side_ports
system.l2cache.cpu_side = system.l2cache.xbar.mem_side_ports
# make the L3 mostly exclusive, and correspondingly ensure that the L2
# writes back also clean lines to the L3
system.l3cache = L3Cache(size="4MB", clusivity="mostly_excl")
system.l3cache = L3Cache(size="4MiB", clusivity="mostly_excl")
system.l3cache.xbar = L2XBar()
system.l2cache.mem_side = system.l3cache.xbar.cpu_side_ports
system.l3cache.cpu_side = system.l3cache.xbar.mem_side_ports

4
configs/dram/low_power_sweep.py
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@@ -116,8 +116,8 @@ system.clk_domain = SrcClockDomain(
clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
)
# We are fine with 256 MB memory for now.
mem_range = AddrRange("256MB")
# We are fine with 256 MiB memory for now.
mem_range = AddrRange("256MiB")
# Start address is 0
system.mem_ranges = [mem_range]

4
configs/dram/sweep.py
View File

@@ -108,8 +108,8 @@ system.clk_domain = SrcClockDomain(
clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
)
# we are fine with 256 MB memory for now
mem_range = AddrRange("256MB")
# we are fine with 256 MiB memory for now
mem_range = AddrRange("256MiB")
system.mem_ranges = [mem_range]
# do not worry about reserving space for the backing store