e1db67c4bd
This commit contains the rest of the base 2 vs base 10 cache/memory size clarifications. It also changes the warning message to use warn(). With these changes, the warning message should now no longer show up during a fresh compilation of gem5. Change-Id: Ia63f841bdf045b76473437f41548fab27dc19631
307 lines
10 KiB
Python
307 lines
10 KiB
Python
# Copyright (c) 2014-2015, 2017, 2019 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import argparse
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import m5
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from m5.objects import *
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from m5.stats import periodicStatDump
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from m5.util import addToPath
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addToPath("../")
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from common import (
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MemConfig,
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ObjectList,
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)
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# This script aims at triggering low power state transitions in the DRAM
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# controller. The traffic generator is used in DRAM mode and traffic
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# states target a different levels of bank utilization and strides.
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# At the end after sweeping through bank utilization and strides, we go
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# through an idle state with no requests to enforce self-refresh.
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parser = argparse.ArgumentParser(
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formatter_class=argparse.ArgumentDefaultsHelpFormatter
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)
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# Use a single-channel DDR4-2400 in 16x4 configuration by default
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parser.add_argument(
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"--mem-type",
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default="DDR4_2400_16x4",
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choices=ObjectList.mem_list.get_names(),
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help="type of memory to use",
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)
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parser.add_argument(
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"--mem-ranks",
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"-r",
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type=int,
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default=1,
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help="Number of ranks to iterate across",
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)
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parser.add_argument(
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"--page-policy",
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"-p",
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choices=["close_adaptive", "open_adaptive"],
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default="close_adaptive",
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help="controller page policy",
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)
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parser.add_argument(
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"--itt-list",
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"-t",
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default="1 20 100",
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help="a list of multipliers for the max value of itt, " 'e.g. "1 20 100"',
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)
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parser.add_argument(
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"--rd-perc", type=int, default=100, help="Percentage of read commands"
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)
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parser.add_argument(
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"--addr-map",
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choices=m5.objects.AddrMap.vals,
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default="RoRaBaCoCh",
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help="DRAM address map policy",
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)
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parser.add_argument(
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"--idle-end",
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type=int,
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default=50000000,
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help="time in ps of an idle period at the end ",
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)
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args = parser.parse_args()
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# Start with the system itself, using a multi-layer 2.0 GHz
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# crossbar, delivering 64 bytes / 3 cycles (one header cycle)
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# which amounts to 42.7 GByte/s per layer and thus per port.
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system = System(membus=IOXBar(width=32))
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system.clk_domain = SrcClockDomain(
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clock="2.0GHz", voltage_domain=VoltageDomain(voltage="1V")
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)
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# We are fine with 256 MiB memory for now.
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mem_range = AddrRange("256MiB")
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# Start address is 0
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system.mem_ranges = [mem_range]
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# Do not worry about reserving space for the backing store
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system.mmap_using_noreserve = True
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# Force a single channel to match the assumptions in the DRAM traffic
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# generator
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args.mem_channels = 1
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args.external_memory_system = 0
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args.tlm_memory = 0
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args.elastic_trace_en = 0
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MemConfig.config_mem(args, system)
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# Sanity check for memory controller class.
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if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
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fatal("This script assumes the controller is a MemCtrl subclass")
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if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
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fatal("This script assumes the memory is a DRAMInterface subclass")
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# There is no point slowing things down by saving any data.
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system.mem_ctrls[0].dram.null = True
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# enable DRAM low power states
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system.mem_ctrls[0].dram.enable_dram_powerdown = True
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# Set the address mapping based on input argument
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system.mem_ctrls[0].dram.addr_mapping = args.addr_map
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system.mem_ctrls[0].dram.page_policy = args.page_policy
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# We create a traffic generator state for each param combination we want to
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# test. Each traffic generator state is specified in the config file and the
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# generator remains in the state for specific period. This period is 0.25 ms.
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# Stats are dumped and reset at the state transition.
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period = 250000000
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# We specify the states in a config file input to the traffic generator.
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cfg_file_name = "lowp_sweep.cfg"
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cfg_file_path = os.path.dirname(__file__) + "/" + cfg_file_name
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cfg_file = open(cfg_file_path, "w")
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# Get the number of banks
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nbr_banks = int(system.mem_ctrls[0].dram.banks_per_rank.value)
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# determine the burst size in bytes
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burst_size = int(
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(
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system.mem_ctrls[0].dram.devices_per_rank.value
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* system.mem_ctrls[0].dram.device_bus_width.value
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* system.mem_ctrls[0].dram.burst_length.value
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)
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/ 8
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)
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# next, get the page size in bytes (the rowbuffer size is already in bytes)
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page_size = (
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system.mem_ctrls[0].dram.devices_per_rank.value
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* system.mem_ctrls[0].dram.device_rowbuffer_size.value
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)
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# Inter-request delay should be such that we can hit as many transitions
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# to/from low power states as possible to. We provide a min and max itt to the
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# traffic generator and it randomises in the range. The parameter is in
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# seconds and we need it in ticks (ps).
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itt_min = system.mem_ctrls[0].dram.tBURST.value * 1000000000000
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# The itt value when set to (tRAS + tRP + tCK) covers the case where
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# a read command is delayed beyond the delay from ACT to PRE_PDN entry of the
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# previous command. For write command followed by precharge, this delay
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# between a write and power down entry will be tRCD + tCL + tWR + tRP + tCK.
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# As we use this delay as a unit and create multiples of it as bigger delays
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# for the sweep, this parameter works for reads, writes and mix of them.
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pd_entry_time = (
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system.mem_ctrls[0].dram.tRAS.value
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+ system.mem_ctrls[0].dram.tRP.value
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+ system.mem_ctrls[0].dram.tCK.value
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) * 1000000000000
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# We sweep itt max using the multipliers specified by the user.
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itt_max_str = args.itt_list.strip().split()
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itt_max_multiples = [int(x) for x in itt_max_str]
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if len(itt_max_multiples) == 0:
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fatal("String for itt-max-list detected empty\n")
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itt_max_values = [pd_entry_time * m for m in itt_max_multiples]
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# Generate request addresses in the entire range, assume we start at 0
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max_addr = mem_range.end
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# For max stride, use min of the page size and 512 bytes as that should be
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# more than enough
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max_stride = min(512, page_size)
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mid_stride = 4 * burst_size
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stride_values = [burst_size, mid_stride, max_stride]
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# be selective about bank utilization instead of going from 1 to the number of
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# banks
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bank_util_values = [1, int(nbr_banks / 2), nbr_banks]
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# Next we create the config file, but first a comment
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cfg_file.write(
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"""# STATE state# period mode=DRAM
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# read_percent start_addr end_addr req_size min_itt max_itt data_limit
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# stride_size page_size #banks #banks_util addr_map #ranks\n"""
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)
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addr_map = m5.objects.AddrMap.map[args.addr_map]
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nxt_state = 0
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for itt_max in itt_max_values:
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for bank in bank_util_values:
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for stride_size in stride_values:
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cfg_file.write(
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"STATE %d %d %s %d 0 %d %d "
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"%d %d %d %d %d %d %d %d %d\n"
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% (
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nxt_state,
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period,
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"DRAM",
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args.rd_perc,
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max_addr,
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burst_size,
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itt_min,
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itt_max,
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0,
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stride_size,
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page_size,
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nbr_banks,
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bank,
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addr_map,
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args.mem_ranks,
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)
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)
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nxt_state = nxt_state + 1
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# State for idle period
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idle_period = args.idle_end
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cfg_file.write("STATE %d %d IDLE\n" % (nxt_state, idle_period))
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# Init state is state 0
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cfg_file.write("INIT 0\n")
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# Go through the states one by one
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for state in range(1, nxt_state + 1):
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cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
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# Transition from last state to itself to not break the probability math
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cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state, nxt_state))
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cfg_file.close()
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# create a traffic generator, and point it to the file we just created
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system.tgen = TrafficGen(config_file=cfg_file_path)
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# add a communication monitor
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system.monitor = CommMonitor()
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# connect the traffic generator to the bus via a communication monitor
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system.tgen.port = system.monitor.cpu_side_port
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system.monitor.mem_side_port = system.membus.cpu_side_ports
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# connect the system port even if it is not used in this example
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system.system_port = system.membus.cpu_side_ports
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# every period, dump and reset all stats
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periodicStatDump(period)
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root = Root(full_system=False, system=system)
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root.system.mem_mode = "timing"
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m5.instantiate()
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# Simulate for exactly as long as it takes to go through all the states
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# This is why sim exists.
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m5.simulate(nxt_state * period + idle_period)
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print("--- Done DRAM low power sweep ---")
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print("Fixed params - ")
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print(
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"\tburst: %d, banks: %d, max stride: %d, itt min: %s ns"
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% (burst_size, nbr_banks, max_stride, itt_min)
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)
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print("Swept params - ")
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print("\titt max multiples input:", itt_max_multiples)
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print("\titt max values", itt_max_values)
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print("\tbank utilization values", bank_util_values)
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print("\tstride values:", stride_values)
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print("Traffic gen config file:", cfg_file_name)
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