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system-arm: Initialize ICC_SRE_EL3 register of all CPUs

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Fix a bug that only CPU0 initialized ICC_SRE_EL3 register.

Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Chun-Chen TK Hsu
2019-10-08 19:02:33 +08:00
parent b1fb2d55c5
commit e1a9794651
1 changed files with 2 additions and 2 deletions
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4
system/arm/aarch64_bootloader/boot.S
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@@ -91,12 +91,12 @@ _start:
str w0, [x1], #4
/* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
2: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
orr x10, x10, #0xf // enable 0xf
msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
isb
2: mov x0, #1
mov x0, #1
msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
#else