derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

configs: Add simpleSystem helper to generate devices.SimpleSystem

Browse Source 
This patch will make it possible to generate a SimpleSystem inheriting
from a configurable base class. More practically it will be possible to
inherit from a baremetal System (ArmSystem) rather than from a
LinuxArmSystem

Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-09-25 13:11:22 +01:00
parent 0f1efb84a3
commit e1488cd05c
3 changed files with 100 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files

180
configs/example/arm/devices.py
View File

@@ -186,106 +186,118 @@ class KvmCluster(CpuCluster):
pass
class SimpleSystem(LinuxArmSystem):
cache_line_size = 64
def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
"""
Create a simple system example. The base class in configurable so
that it is possible (e.g) to link the platform (hardware configuration)
with a baremetal ArmSystem or with a LinuxArmSystem.
"""
class SimpleSystem(BaseSystem):
cache_line_size = 64
def __init__(self, caches, mem_size, platform=None, **kwargs):
super(SimpleSystem, self).__init__(**kwargs)
def __init__(self, caches, mem_size, platform=None, **kwargs):
super(SimpleSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(clock="1GHz",
voltage_domain=Parent.voltage_domain)
self.voltage_domain = VoltageDomain(voltage="1.0V")
self.clk_domain = SrcClockDomain(
clock="1GHz",
voltage_domain=Parent.voltage_domain)
if platform is None:
self.realview = VExpress_GEM5_V1()
else:
self.realview = platform
if platform is None:
self.realview = VExpress_GEM5_V1()
else:
self.realview = platform
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.flags_addr = self.realview.realview_io.pio_addr + 0x30
self.membus = MemBus()
self.membus = MemBus()
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
self.intrctrl = IntrControl()
self.terminal = Terminal()
self.vncserver = VncServer()
self.iobus = IOXBar()
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
assert long(mem_range.size()) >= long(Addr(mem_size))
self.mem_ranges = [ AddrRange(start=mem_range.start, size=mem_size) ]
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
else:
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
self.iobus = IOXBar()
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
assert long(mem_range.size()) >= long(Addr(mem_size))
self.mem_ranges = [
AddrRange(start=mem_range.start, size=mem_size) ]
self._pci_devices = 0
self._clusters = []
self._num_cpus = 0
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
else:
self.dmabridge = Bridge(delay='50ns',
ranges=[self.mem_ranges[0]])
def attach_pci(self, dev):
dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
self._pci_devices += 1
self.realview.attachPciDevice(dev, self.iobus)
self._pci_devices = 0
self._clusters = []
self._num_cpus = 0
def connect(self):
self.iobridge.master = self.iobus.slave
self.iobridge.slave = self.membus.master
def attach_pci(self, dev):
dev.pci_bus, dev.pci_dev, dev.pci_func = \
(0, self._pci_devices + 1, 0)
self._pci_devices += 1
self.realview.attachPciDevice(dev, self.iobus)
if self._caches:
self.iocache.mem_side = self.membus.slave
self.iocache.cpu_side = self.iobus.master
else:
self.dmabridge.master = self.membus.slave
self.dmabridge.slave = self.iobus.master
def connect(self):
self.iobridge.master = self.iobus.slave
self.iobridge.slave = self.membus.master
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.realview.attachOnChipIO(self.membus, self.iobridge)
self.realview.attachIO(self.iobus)
self.system_port = self.membus.slave
if self._caches:
self.iocache.mem_side = self.membus.slave
self.iocache.cpu_side = self.iobus.master
else:
self.dmabridge.master = self.membus.slave
self.dmabridge.slave = self.iobus.master
def numCpuClusters(self):
return len(self._clusters)
if hasattr(self.realview.gic, 'cpu_addr'):
self.gic_cpu_addr = self.realview.gic.cpu_addr
self.realview.attachOnChipIO(self.membus, self.iobridge)
self.realview.attachIO(self.iobus)
self.system_port = self.membus.slave
def addCpuCluster(self, cpu_cluster, num_cpus):
assert cpu_cluster not in self._clusters
assert num_cpus > 0
self._clusters.append(cpu_cluster)
self._num_cpus += num_cpus
def numCpuClusters(self):
return len(self._clusters)
def numCpus(self):
return self._num_cpus
def addCpuCluster(self, cpu_cluster, num_cpus):
assert cpu_cluster not in self._clusters
assert num_cpus > 0
self._clusters.append(cpu_cluster)
self._num_cpus += num_cpus
def numCpus(self):
return self._num_cpus
def addCaches(self, need_caches, last_cache_level):
if not need_caches:
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.connectMemSide(self.membus)
return
cluster_mem_bus = self.membus
assert last_cache_level >= 1 and last_cache_level <= 3
for cluster in self._clusters:
cluster.addL1()
if last_cache_level > 1:
for cluster in self._clusters:
cluster.addL2(cluster.clk_domain)
if last_cache_level > 2:
max_clock_cluster = max(self._clusters,
key=lambda c: c.clk_domain.clock[0])
self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
self.toL3Bus = L2XBar(width=64)
self.toL3Bus.master = self.l3.cpu_side
self.l3.mem_side = self.membus.slave
cluster_mem_bus = self.toL3Bus
def addCaches(self, need_caches, last_cache_level):
if not need_caches:
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.connectMemSide(self.membus)
return
cluster.connectMemSide(cluster_mem_bus)
cluster_mem_bus = self.membus
assert last_cache_level >= 1 and last_cache_level <= 3
for cluster in self._clusters:
cluster.addL1()
if last_cache_level > 1:
for cluster in self._clusters:
cluster.addL2(cluster.clk_domain)
if last_cache_level > 2:
max_clock_cluster = max(self._clusters,
key=lambda c: c.clk_domain.clock[0])
self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
self.toL3Bus = L2XBar(width=64)
self.toL3Bus.master = self.l3.cpu_side
self.l3.mem_side = self.membus.slave
cluster_mem_bus = self.toL3Bus
# connect each cluster to the memory hierarchy
for cluster in self._clusters:
cluster.connectMemSide(cluster_mem_bus)
return SimpleSystem(caches, mem_size, platform, **kwargs)

3
configs/example/arm/fs_bigLITTLE.py
View File

@@ -119,7 +119,8 @@ def createSystem(caches, kernel, bootscript,
platform = ObjectList.platform_list.get(machine_type)
m5.util.inform("Simulated platform: %s", platform.__name__)
sys = devices.SimpleSystem(caches, default_mem_size, platform(),
sys = devices.simpleSystem(LinuxArmSystem,
caches, default_mem_size, platform(),
kernel=SysPaths.binary(kernel),
readfile=bootscript)

3
configs/example/arm/starter_fs.py
View File

@@ -104,7 +104,8 @@ def create(args):
# Only simulate caches when using a timing CPU (e.g., the HPI model)
want_caches = True if mem_mode == "timing" else False
system = devices.SimpleSystem(want_caches,
system = devices.simpleSystem(LinuxArmSystem,
want_caches,
args.mem_size,
mem_mode=mem_mode,
kernel=SysPaths.binary(args.kernel),