arch-arm: Add system registers added/used by SME

We add the following registers which are added by SME:

* ID_AA64SMFR0_EL1
* SVCR
* SMIDR_EL1
* SMPRI_EL1
* SMPRIMAP_EL2
* SMCR_EL3
* SMCR_EL2
* SMCR_EL12
* SMCR_EL1
* TPIDR2_EL0
* MPAMSM_EL1

In addition we extend some of the existing registers with SME support
(SCR_EL3, CPACR_EL1, CPTR_EL2, CPTR_EL3, etc). These regisers are
responsible for enabling SME itself, or for configuring the trapping
behaviour for the differernt ELs.

In addition we implement some dummy registers as they are officially
required by SME, but gem5 itself doesn't actually support the features
yet (FGT, HCX).

Jira Issue: https://gem5.atlassian.net/browse/GEM5-1289

Change-Id: I18ba65fb9ac2b7a4b4f361998564fb5d472d1789
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64335
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/arch/arm/ArmSystem.py

@@ -49,6 +49,21 @@ class SveVectorLength(UInt8):
     max = 16
 
 
+class SmeVectorLength(UInt8):
+    min = 1
+    max = 16
+
+    def _check(self):
+        super()._check()
+
+        # SME needs to be a whole power of 2. We already know value is
+        # not zero. Hence:
+        if self.value & (self.value - 1) != 0:
+            raise TypeError(
+                "SME vector length is not a power of 2: %d" % self.value
+            )
+
+
 class ArmExtension(ScopedEnum):
     vals = [
         # Armv8.1
@@ -69,6 +84,8 @@ class ArmExtension(ScopedEnum):
         "FEAT_PAuth",
         # Armv8.4
         "FEAT_SEL2",
+        # Armv9.2
+        "FEAT_SME",  # Optional in Armv9.2
         # Others
         "SECURITY",
         "LPAE",
@@ -145,6 +162,8 @@ class ArmDefaultRelease(Armv8):
         "FEAT_PAuth",
         # Armv8.4
         "FEAT_SEL2",
+        # Armv9.2
+        "FEAT_SME",
     ]
 
 
@@ -176,6 +195,10 @@ class Armv84(Armv83):
     extensions = Armv83.extensions + ["FEAT_SEL2"]
 
 
+class Armv92(Armv84):
+    extensions = Armv84.extensions + ["FEAT_SME"]
+
+
 class ArmSystem(System):
     type = "ArmSystem"
     cxx_header = "arch/arm/system.hh"
@@ -205,6 +228,9 @@ class ArmSystem(System):
     sve_vl = Param.SveVectorLength(
         1, "SVE vector length in quadwords (128-bit)"
     )
+    sme_vl = Param.SveVectorLength(
+        1, "SME vector length in quadwords (128-bit)"
+    )
     semihosting = Param.ArmSemihosting(
         NULL,
         "Enable support for the Arm semihosting by settings this parameter",