diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index 4f336e04cd..e73046d08b 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2013, 2015-2021 ARM Limited
+# Copyright (c) 2012-2013, 2015-2022 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -38,7 +38,7 @@ from m5.proxy import *
 
 from m5.SimObject import SimObject
 from m5.objects.ArmPMU import ArmPMU
-from m5.objects.ArmSystem import SveVectorLength, ArmRelease
+from m5.objects.ArmSystem import SveVectorLength, SmeVectorLength, ArmRelease
 from m5.objects.BaseISA import BaseISA
 
 # Enum for DecoderFlavor
@@ -58,6 +58,8 @@ class ArmDefaultSERelease(ArmRelease):
         "FEAT_FCMA",
         "FEAT_JSCVT",
         "FEAT_PAuth",
+        # Armv9.2
+        "FEAT_SME",
         # Other
         "TME",
     ]
@@ -160,11 +162,14 @@ class ArmISA(BaseISA):
         "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP",
     )
 
-    # This is required because in SE mode a generic System SimObject is
-    # allocated, instead of an ArmSystem
+    # These are required because in SE mode a generic System SimObject
+    # is allocated, instead of an ArmSystem
     sve_vl_se = Param.SveVectorLength(
         1, "SVE vector length in quadwords (128-bit), SE-mode only"
     )
+    sme_vl_se = Param.SmeVectorLength(
+        1, "SME vector length in quadwords (128-bit), SE-mode only"
+    )
 
     # Recurse into subnodes to generate DTB entries. This is mainly needed to
     # generate the PMU entry.
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 936c032780..25cf8b2172 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -49,6 +49,21 @@ class SveVectorLength(UInt8):
     max = 16
 
 
+class SmeVectorLength(UInt8):
+    min = 1
+    max = 16
+
+    def _check(self):
+        super()._check()
+
+        # SME needs to be a whole power of 2. We already know value is
+        # not zero. Hence:
+        if self.value & (self.value - 1) != 0:
+            raise TypeError(
+                "SME vector length is not a power of 2: %d" % self.value
+            )
+
+
 class ArmExtension(ScopedEnum):
     vals = [
         # Armv8.1
@@ -69,6 +84,8 @@ class ArmExtension(ScopedEnum):
         "FEAT_PAuth",
         # Armv8.4
         "FEAT_SEL2",
+        # Armv9.2
+        "FEAT_SME",  # Optional in Armv9.2
         # Others
         "SECURITY",
         "LPAE",
@@ -145,6 +162,8 @@ class ArmDefaultRelease(Armv8):
         "FEAT_PAuth",
         # Armv8.4
         "FEAT_SEL2",
+        # Armv9.2
+        "FEAT_SME",
     ]
 
 
@@ -176,6 +195,10 @@ class Armv84(Armv83):
     extensions = Armv83.extensions + ["FEAT_SEL2"]
 
 
+class Armv92(Armv84):
+    extensions = Armv84.extensions + ["FEAT_SME"]
+
+
 class ArmSystem(System):
     type = "ArmSystem"
     cxx_header = "arch/arm/system.hh"
@@ -205,6 +228,9 @@ class ArmSystem(System):
     sve_vl = Param.SveVectorLength(
         1, "SVE vector length in quadwords (128-bit)"
     )
+    sme_vl = Param.SveVectorLength(
+        1, "SME vector length in quadwords (128-bit)"
+    )
     semihosting = Param.ArmSemihosting(
         NULL,
         "Enable support for the Arm semihosting by settings this parameter",
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index c6bb2bd8d1..78a1f4fc9f 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -110,6 +110,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = system->haveLargeAsid64();
         physAddrRange = system->physAddrRange();
         sveVL = system->sveVL();
+        smeVL = system->smeVL();
 
         release = system->releaseFS();
     } else {
@@ -117,6 +118,7 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
         haveLargeAsid64 = false;
         physAddrRange = 32;  // dummy value
         sveVL = p.sve_vl_se;
+        smeVL = p.sme_vl_se;
 
         release = p.release_se;
     }
@@ -406,6 +408,49 @@ ISA::initID64(const ArmISAParams &p)
         miscRegs[MISCREG_ZCR_EL1] = sveVL - 1;
     }
 
+    // SME
+
+    // Set up the SME SMIDR
+    // [63:32] RES0
+    // [31:24] Implementer - default this to Arm Limited
+    // [23:16] SMCU Revision - set to 0 as we don't model an SMCU
+    // [15]    SMPS - We don't do priorities in gem5, so disable
+    // [14:12] RES0
+    // [11:0]  Affinity - we implement per-CPU SME, so set to 0 (no SMCU)
+    miscRegs[MISCREG_SMIDR_EL1] = 0 | // Affinity
+        0 << 15 |                     // SMPS
+        0x41 << 24;                   // Implementer
+
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] = 0;
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // F32F32
+    // The following BF16F32 is actually not implemented due to a lack
+    // of BF16 support in gem5's fplib. However, as per the SME spec the
+    // _only_ allowed value is 0x1.
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 34; // BF16F32
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 35; // F16F32
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 36; // I8I32
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 48; // F64F64
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0xFUL << 52; // I16I64
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x0UL << 56; // SMEver
+    miscRegs[MISCREG_ID_AA64SMFR0_EL1] |= 0x1UL << 32; // FA64
+
+    // We want to support FEAT_SME_FA64. Therefore, we enable it in all
+    // SMCR_ELx registers by default. Runtime software might change this
+    // later, but given that gem5 doesn't disable instructions based on
+    // this flag we default to the most representative value.
+    miscRegs[MISCREG_SMCR_EL3] = 0x1 << 31;
+    miscRegs[MISCREG_SMCR_EL2] = 0x1 << 31;
+    miscRegs[MISCREG_SMCR_EL1] = 0x1 << 31;
+
+    // Set the vector default vector length
+    if (release->has(ArmExtension::SECURITY)) {
+        miscRegs[MISCREG_SMCR_EL3] |= ((smeVL - 1) & 0xF);
+    } else if (release->has(ArmExtension::VIRTUALIZATION)) {
+        miscRegs[MISCREG_SMCR_EL2] |= ((smeVL - 1) & 0xF);
+    } else {
+        miscRegs[MISCREG_SMCR_EL1] |= ((smeVL - 1) & 0xF);
+    }
+
     // Enforce consistency with system-level settings...
 
     // EL3
@@ -420,6 +465,10 @@ ISA::initID64(const ArmISAParams &p)
     miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32,
         release->has(ArmExtension::FEAT_SVE) ? 0x1 : 0x0);
+    // SME
+    miscRegs[MISCREG_ID_AA64PFR1_EL1] = insertBits(
+        miscRegs[MISCREG_ID_AA64PFR1_EL1], 27, 24,
+        release->has(ArmExtension::FEAT_SME) ? 0x1 : 0x0);
     // SecEL2
     miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
         miscRegs[MISCREG_ID_AA64PFR0_EL1], 39, 36,
@@ -962,6 +1011,10 @@ ISA::readMiscReg(RegIndex idx)
         {
             return miscRegs[MISCREG_CPSR] & 0x800000;
         }
+      case MISCREG_SVCR:
+        {
+            return miscRegs[MISCREG_SVCR];
+        }
       case MISCREG_L2CTLR:
         {
             // mostly unimplemented, just set NumCPUs field from sim and return
@@ -1037,7 +1090,9 @@ ISA::readMiscReg(RegIndex idx)
                     0x0000001000000000 : 0) | // SecEL2
                (gicv3CpuInterface     ? 0x0000000001000000 : 0);
       case MISCREG_ID_AA64PFR1_EL1:
-        return 0; // bits [63:0] RES0 (reserved for future use)
+        return 0x0 |
+               (release->has(ArmExtension::FEAT_SME) ?
+                    0x1 << 24 : 0); // SME
 
       // Generic Timer registers
       case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
@@ -1188,6 +1243,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 if (release->has(ArmExtension::FEAT_SVE)) {
                     cpacrMask.zen = ones;
                 }
+                if (release->has(ArmExtension::FEAT_SME)) {
+                    cpacrMask.smen = ones;
+                }
                 newVal &= cpacrMask;
                 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
                         miscRegName[idx], newVal);
@@ -1205,14 +1263,21 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                     cptrMask.tz = ones;
                     cptrMask.zen = hcr.e2h ? ones : 0;
                 }
+                if (release->has(ArmExtension::FEAT_SME)) {
+                    cptrMask.tsm = ones;
+                    cptrMask.smen = hcr.e2h ? ones : 0;
+                }
                 cptrMask.fpen = hcr.e2h ? ones : 0;
                 newVal &= cptrMask;
                 cptrMask = 0;
-                cptrMask.res1_13_12_el2 = ones;
+                cptrMask.res1_13_el2 = ones;
                 cptrMask.res1_7_0_el2 = ones;
                 if (!release->has(ArmExtension::FEAT_SVE)) {
                     cptrMask.res1_8_el2 = ones;
                 }
+                if (!release->has(ArmExtension::FEAT_SME)) {
+                    cptrMask.res1_12_el2 = ones;
+                }
                 cptrMask.res1_9_el2 = ones;
                 newVal |= cptrMask;
                 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
@@ -1229,6 +1294,9 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 if (release->has(ArmExtension::FEAT_SVE)) {
                     cptrMask.ez = ones;
                 }
+                if (release->has(ArmExtension::FEAT_SME)) {
+                    cptrMask.esm = ones;
+                }
                 newVal &= cptrMask;
                 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
                         miscRegName[idx], newVal);
@@ -1917,6 +1985,21 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
                 idx = MISCREG_CPSR;
             }
             break;
+          case MISCREG_SVCR:
+            {
+                SVCR svcr = miscRegs[MISCREG_SVCR];
+                SVCR newSvcr = newVal;
+
+                // Don't allow other bits to be set
+                svcr.sm = newSvcr.sm;
+                svcr.za = newSvcr.za;
+                newVal = svcr;
+            }
+            break;
+          case MISCREG_SMPRI_EL1:
+            // Only the bottom 4 bits are settable
+            newVal = newVal & 0xF;
+            break;
           case MISCREG_AT_S1E1R_Xt:
             addressTranslation64(MMU::S1E1Tran, BaseMMU::Read, 0, val);
             return;
@@ -1982,6 +2065,16 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
             tc->getDecoderPtr()->as<Decoder>().setSveLen(
                     (getCurSveVecLenInBits() >> 7) - 1);
             return;
+          case MISCREG_SMCR_EL3:
+          case MISCREG_SMCR_EL2:
+          case MISCREG_SMCR_EL1:
+            // Set the value here as we need to update the regs before
+            // reading them back in getCurSmeVecLenInBits (not
+            // implemented yet) to avoid setting stale vector lengths in
+            // the decoder.
+            setMiscRegNoEffect(idx, newVal);
+            // TODO: set the SME vector length
+            return;
         }
         setMiscRegNoEffect(idx, newVal);
     }
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 6f9478298d..bc0ab7683e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -96,6 +96,9 @@ namespace ArmISA
         /** SVE vector length in quadwords */
         unsigned sveVL;
 
+        /** SME vector length in quadwords */
+        unsigned smeVL;
+
         /** This could be either a FS or a SE release */
         const ArmRelease *release;
 
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 142b25f8c4..382b63e8bd 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -912,7 +912,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 0, 0, 4, 2), MISCREG_RAZ },
     { MiscRegNum64(3, 0, 0, 4, 3), MISCREG_RAZ },
     { MiscRegNum64(3, 0, 0, 4, 4), MISCREG_ID_AA64ZFR0_EL1 },
-    { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_RAZ },
+    { MiscRegNum64(3, 0, 0, 4, 5), MISCREG_ID_AA64SMFR0_EL1 },
     { MiscRegNum64(3, 0, 0, 4, 6), MISCREG_RAZ },
     { MiscRegNum64(3, 0, 0, 4, 7), MISCREG_RAZ },
     { MiscRegNum64(3, 0, 0, 5, 0), MISCREG_ID_AA64DFR0_EL1 },
@@ -943,6 +943,8 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 0, 1, 0, 1), MISCREG_ACTLR_EL1 },
     { MiscRegNum64(3, 0, 1, 0, 2), MISCREG_CPACR_EL1 },
     { MiscRegNum64(3, 0, 1, 2, 0), MISCREG_ZCR_EL1 },
+    { MiscRegNum64(3, 0, 1, 2, 4), MISCREG_SMPRI_EL1 },
+    { MiscRegNum64(3, 0, 1, 2, 6), MISCREG_SMCR_EL1 },
     { MiscRegNum64(3, 0, 2, 0, 0), MISCREG_TTBR0_EL1 },
     { MiscRegNum64(3, 0, 2, 0, 1), MISCREG_TTBR1_EL1 },
     { MiscRegNum64(3, 0, 2, 0, 2), MISCREG_TCR_EL1 },
@@ -981,6 +983,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 0, 9, 14, 2), MISCREG_PMINTENCLR_EL1 },
     { MiscRegNum64(3, 0, 10, 2, 0), MISCREG_MAIR_EL1 },
     { MiscRegNum64(3, 0, 10, 3, 0), MISCREG_AMAIR_EL1 },
+    { MiscRegNum64(3, 0, 10, 5, 3), MISCREG_MPAMSM_EL1 },
     { MiscRegNum64(3, 0, 12, 0, 0), MISCREG_VBAR_EL1 },
     { MiscRegNum64(3, 0, 12, 0, 1), MISCREG_RVBAR_EL1 },
     { MiscRegNum64(3, 0, 12, 1, 0), MISCREG_ISR_EL1 },
@@ -1024,6 +1027,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 0, 15, 1, 4), MISCREG_DL1DATA4_EL1 },
     { MiscRegNum64(3, 1, 0, 0, 0), MISCREG_CCSIDR_EL1 },
     { MiscRegNum64(3, 1, 0, 0, 1), MISCREG_CLIDR_EL1 },
+    { MiscRegNum64(3, 1, 0, 0, 6), MISCREG_SMIDR_EL1 },
     { MiscRegNum64(3, 1, 0, 0, 7), MISCREG_AIDR_EL1 },
     { MiscRegNum64(3, 1, 11, 0, 2), MISCREG_L2CTLR_EL1 },
     { MiscRegNum64(3, 1, 11, 0, 3), MISCREG_L2ECTLR_EL1 },
@@ -1038,6 +1042,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
     { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
     { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
+    { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
     { MiscRegNum64(3, 3, 4, 4, 0), MISCREG_FPCR },
     { MiscRegNum64(3, 3, 4, 4, 1), MISCREG_FPSR },
     { MiscRegNum64(3, 3, 4, 5, 0), MISCREG_DSPSR_EL0 },
@@ -1057,6 +1062,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 3, 9, 14, 3), MISCREG_PMOVSSET_EL0 },
     { MiscRegNum64(3, 3, 13, 0, 2), MISCREG_TPIDR_EL0 },
     { MiscRegNum64(3, 3, 13, 0, 3), MISCREG_TPIDRRO_EL0 },
+    { MiscRegNum64(3, 3, 13, 0, 5), MISCREG_TPIDR2_EL0 },
     { MiscRegNum64(3, 3, 14, 0, 0), MISCREG_CNTFRQ_EL0 },
     { MiscRegNum64(3, 3, 14, 0, 1), MISCREG_CNTPCT_EL0 },
     { MiscRegNum64(3, 3, 14, 0, 2), MISCREG_CNTVCT_EL0 },
@@ -1087,8 +1093,13 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 4, 1, 1, 1), MISCREG_MDCR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 2), MISCREG_CPTR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 3), MISCREG_HSTR_EL2 },
+    { MiscRegNum64(3, 4, 1, 1, 4), MISCREG_HFGRTR_EL2 },
+    { MiscRegNum64(3, 4, 1, 1, 5), MISCREG_HFGWTR_EL2 },
     { MiscRegNum64(3, 4, 1, 1, 7), MISCREG_HACR_EL2 },
     { MiscRegNum64(3, 4, 1, 2, 0), MISCREG_ZCR_EL2 },
+    { MiscRegNum64(3, 4, 1, 2, 2), MISCREG_HCRX_EL2 },
+    { MiscRegNum64(3, 4, 1, 2, 5), MISCREG_SMPRIMAP_EL2 },
+    { MiscRegNum64(3, 4, 1, 2, 6), MISCREG_SMCR_EL2 },
     { MiscRegNum64(3, 4, 2, 0, 0), MISCREG_TTBR0_EL2 },
     { MiscRegNum64(3, 4, 2, 0, 1), MISCREG_TTBR1_EL2 },
     { MiscRegNum64(3, 4, 2, 0, 2), MISCREG_TCR_EL2 },
@@ -1167,6 +1178,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 5, 1, 0, 0), MISCREG_SCTLR_EL12 },
     { MiscRegNum64(3, 5, 1, 0, 2), MISCREG_CPACR_EL12 },
     { MiscRegNum64(3, 5, 1, 2, 0), MISCREG_ZCR_EL12 },
+    { MiscRegNum64(3, 5, 1, 2, 6), MISCREG_SMCR_EL12 },
     { MiscRegNum64(3, 5, 2, 0, 0), MISCREG_TTBR0_EL12 },
     { MiscRegNum64(3, 5, 2, 0, 1), MISCREG_TTBR1_EL12 },
     { MiscRegNum64(3, 5, 2, 0, 2), MISCREG_TCR_EL12 },
@@ -1193,6 +1205,7 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 6, 1, 1, 1), MISCREG_SDER32_EL3 },
     { MiscRegNum64(3, 6, 1, 1, 2), MISCREG_CPTR_EL3 },
     { MiscRegNum64(3, 6, 1, 2, 0), MISCREG_ZCR_EL3 },
+    { MiscRegNum64(3, 6, 1, 2, 6), MISCREG_SMCR_EL3 },
     { MiscRegNum64(3, 6, 1, 3, 1), MISCREG_MDCR_EL3 },
     { MiscRegNum64(3, 6, 2, 0, 0), MISCREG_TTBR0_EL3 },
     { MiscRegNum64(3, 6, 2, 0, 2), MISCREG_TCR_EL3 },
@@ -4932,6 +4945,30 @@ ISA::initializeMiscRegMetadata()
         .fault(EL3, faultZcrEL3)
         .allPrivileges().exceptUserMode();
 
+    // SME
+    InitReg(MISCREG_ID_AA64SMFR0_EL1)
+        .allPrivileges().exceptUserMode().writes(0);
+    InitReg(MISCREG_SVCR)
+        .allPrivileges();
+    InitReg(MISCREG_SMIDR_EL1)
+        .allPrivileges().exceptUserMode().writes(0);
+    InitReg(MISCREG_SMPRI_EL1)
+        .allPrivileges().exceptUserMode().reads(1);
+    InitReg(MISCREG_SMPRIMAP_EL2)
+        .hyp().mon();
+    InitReg(MISCREG_SMCR_EL3)
+        .mon();
+    InitReg(MISCREG_SMCR_EL2)
+        .hyp().mon();
+    InitReg(MISCREG_SMCR_EL12)
+        .allPrivileges().exceptUserMode();
+    InitReg(MISCREG_SMCR_EL1)
+        .allPrivileges().exceptUserMode();
+    InitReg(MISCREG_TPIDR2_EL0)
+        .allPrivileges();
+    InitReg(MISCREG_MPAMSM_EL1)
+        .allPrivileges().exceptUserMode();
+
     // Dummy registers
     InitReg(MISCREG_NOP)
       .allPrivileges();
@@ -4979,6 +5016,19 @@ ISA::initializeMiscRegMetadata()
       .warnNotFail()
       .fault(faultUnimplemented);
 
+    // HCX extension (unimplemented)
+    InitReg(MISCREG_HCRX_EL2)
+      .unimplemented()
+      .warnNotFail();
+
+    // FGT extension (unimplemented)
+    InitReg(MISCREG_HFGRTR_EL2)
+      .unimplemented()
+      .warnNotFail();
+    InitReg(MISCREG_HFGWTR_EL2)
+      .unimplemented()
+      .warnNotFail();
+
     // Register mappings for some unimplemented registers:
     // ESR_EL1 -> DFSR
     // RMR_EL1 -> RMR
diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh
index 0b61eec2d6..999993b0de 100644
--- a/src/arch/arm/regs/misc.hh
+++ b/src/arch/arm/regs/misc.hh
@@ -1062,6 +1062,19 @@ namespace ArmISA
         MISCREG_ZCR_EL12,
         MISCREG_ZCR_EL1,
 
+        // SME
+        MISCREG_ID_AA64SMFR0_EL1,
+        MISCREG_SVCR,
+        MISCREG_SMIDR_EL1,
+        MISCREG_SMPRI_EL1,
+        MISCREG_SMPRIMAP_EL2,
+        MISCREG_SMCR_EL3,
+        MISCREG_SMCR_EL2,
+        MISCREG_SMCR_EL12,
+        MISCREG_SMCR_EL1,
+        MISCREG_TPIDR2_EL0,
+        MISCREG_MPAMSM_EL1,
+
         // NUM_PHYS_MISCREGS specifies the number of actual physical
         // registers, not considering the following pseudo-registers
         // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -1092,6 +1105,13 @@ namespace ArmISA
         MISCREG_VSESR_EL2,
         MISCREG_VDISR_EL2,
 
+        // HCX extension (unimplemented)
+        MISCREG_HCRX_EL2,
+
+        // FGT extension (unimplemented)
+        MISCREG_HFGRTR_EL2,
+        MISCREG_HFGWTR_EL2,
+
         // PSTATE
         MISCREG_PAN,
         MISCREG_UAO,
@@ -2684,6 +2704,18 @@ namespace ArmISA
         "zcr_el12",
         "zcr_el1",
 
+        "id_aa64smfr0_el1",
+        "svcr",
+        "smidr_el1",
+        "smpri_el1",
+        "smprimap_el2",
+        "smcr_el3",
+        "smcr_el2",
+        "smcr_el12",
+        "smcr_el1",
+        "tpidr2_el0",
+        "mpamsm_el1",
+
         "num_phys_regs",
 
         // Dummy registers
@@ -2702,6 +2734,9 @@ namespace ArmISA
         "disr_el1",
         "vsesr_el2",
         "vdisr_el2",
+        "hcrx_el2",
+        "hfgrtr_el2",
+        "hfgwtr_el2",
 
         // PSTATE
         "pan",
diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh
index 05bf19bf5a..0fe5a00ae8 100644
--- a/src/arch/arm/regs/misc_types.hh
+++ b/src/arch/arm/regs/misc_types.hh
@@ -416,6 +416,7 @@ namespace ArmISA
         Bitfield<21, 20> cp10;
         Bitfield<21, 20> fpen;  // AArch64
         Bitfield<23, 22> cp11;
+        Bitfield<25, 24> smen; // SME
         Bitfield<25, 24> cp12;
         Bitfield<27, 26> cp13;
         Bitfield<29, 28> rsvd;
@@ -734,10 +735,14 @@ namespace ArmISA
         Bitfield<31> tcpac;
         Bitfield<30> tam;
         Bitfield<28> tta_e2h;
+        Bitfield<25, 24> smen;
         Bitfield<21, 20> fpen;
         Bitfield<20> tta;
         Bitfield<17, 16> zen;
-        Bitfield<13, 12> res1_13_12_el2;
+        Bitfield<13, 13> res1_13_el2;
+        Bitfield<12, 12> res1_12_el2;
+        Bitfield<12> esm;  // SME (CPTR_EL3)
+        Bitfield<12> tsm;  // SME (CPTR_EL2)
         Bitfield<10> tfp;
         Bitfield<9> res1_9_el2;
         Bitfield<8> res1_8_el2;
@@ -750,6 +755,34 @@ namespace ArmISA
         Bitfield<3, 0> len;
     EndBitUnion(ZCR)
 
+    BitUnion64(SMCR)
+        Bitfield<63, 32> res0_63_32;
+        Bitfield<31, 31> fa64;
+        Bitfield<30, 9> res0_30_9;
+        Bitfield<8, 4> razwi_8_4;
+        Bitfield<3, 0> len;
+    EndBitUnion(SMCR)
+
+    BitUnion64(SVCR)
+        Bitfield<63, 2> res0_63_2;
+        Bitfield<1, 1> za;
+        Bitfield<0, 0> sm;
+    EndBitUnion(SVCR)
+
+    BitUnion64(SMIDR)
+        Bitfield<63, 32> res0_63_32;
+        Bitfield<31, 24> implementer;
+        Bitfield<23, 16> revision;
+        Bitfield<15, 15> smps;
+        Bitfield<14, 12> res0_14_12;
+        Bitfield<11, 0>  affinity;
+    EndBitUnion(SMIDR)
+
+    BitUnion64(SMPRI)
+        Bitfield<63, 4> res0_63_4;
+        Bitfield<3, 0> priority;
+    EndBitUnion(SMPRI)
+
    BitUnion32(OSL)
         Bitfield<64, 4> res0;
         Bitfield<3> oslm_3;
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 747695f16e..d6e28e70d9 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -78,6 +78,7 @@ ArmSystem::ArmSystem(const Params &p)
       _physAddrRange64(p.phys_addr_range_64),
       _haveLargeAsid64(p.have_large_asid_64),
       _sveVL(p.sve_vl),
+      _smeVL(p.sme_vl),
       semihosting(p.semihosting),
       release(p.release),
       multiProc(p.multi_proc)
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index a712615b6e..7b0e6be322 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2015-2022 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -128,6 +128,9 @@ class ArmSystem : public System
     /** SVE vector length at reset, in quadwords */
     const unsigned _sveVL;
 
+    /** SME vector length at reset, in quadwords */
+    const unsigned _smeVL;
+
     /**
      * True if the Semihosting interface is enabled.
      */
@@ -205,6 +208,9 @@ class ArmSystem : public System
     /** Returns the SVE vector length at reset, in quadwords */
     unsigned sveVL() const { return _sveVL; }
 
+    /** Returns the SME vector length at reset, in quadwords */
+    unsigned smeVL() const { return _smeVL; }
+
     /** Returns the supported physical address range in bits if the highest
      * implemented exception level is 64 bits (ARMv8) */
     uint8_t physAddrRange64() const { return _physAddrRange64; }