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arch-arm: AArch64 Crypto AES

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This patch implements the AArch64 AES instructions
from the Crypto extension.

Change-Id: I9143041ec7e1c6a50dcad3f72d7d1b55d6f2d402
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13250
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-05-09 11:52:05 +01:00
parent 52bab3f6eb
commit dd63d6d932
3 changed files with 43 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/isa/formats/aarch64.isa
View File

@@ -1467,6 +1467,8 @@ namespace Aarch64
return decodeNeon3Diff(machInst);
} else if (bits(machInst, 20, 17) == 0x0) {
return decodeNeon2RegMisc(machInst);
} else if (bits(machInst, 20, 17) == 0x4) {
return decodeCryptoAES(machInst);
} else if (bits(machInst, 20, 17) == 0x8) {
return decodeNeonAcrossLanes(machInst);
} else {

26
src/arch/arm/isa/formats/crypto64.isa
View File

@@ -39,6 +39,9 @@
let {{
header_output = '''
StaticInstPtr
decodeCryptoAES(ExtMachInst machInst);
StaticInstPtr
decodeCryptoThreeRegSHA(ExtMachInst machInst);
@@ -48,6 +51,29 @@ let {{
decoder_output = '''
StaticInstPtr
decodeCryptoAES(ExtMachInst machInst)
{
const auto opcode = bits(machInst, 16, 12);
const auto size = bits(machInst, 23, 22);
IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
if (size) {
// UNALLOCATED
return new Unknown64(machInst);
} else {
switch (opcode) {
case 0x4: return new AESE64(machInst, rd, rd, rn);
case 0x5: return new AESD64(machInst, rd, rd, rn);
case 0x6: return new AESMC64(machInst, rd, rn);
case 0x7: return new AESIMC64(machInst, rd, rn);
default: return new Unknown64(machInst);
}
}
}
StaticInstPtr
decodeCryptoTwoRegSHA(ExtMachInst machInst)
{

15
src/arch/arm/isa/insts/crypto64.isa
View File

@@ -120,6 +120,11 @@ let {{
decoder_output += RegRegOpConstructor.subst(cryptoiop)
exec_output += CryptoPredOpExecute.subst(cryptoiop)
aeseCode = "crypto.aesEncrypt(output, input, input2);"
aesdCode = "crypto.aesDecrypt(output, input, input2);"
aesmcCode = "crypto.aesMixColumns(output, input);"
aesimcCode = "crypto.aesInvMixColumns(output, input);"
sha1_cCode = "crypto.sha1C(output, input, input2);"
sha1_pCode = "crypto.sha1P(output, input, input2);"
sha1_mCode = "crypto.sha1M(output, input, input2);"
@@ -132,6 +137,16 @@ let {{
sha256_su0Code = "crypto.sha256Su0(output, input);"
sha256_su1Code = "crypto.sha256Su1(output, input, input2);"
aes_enabled = cryptoEnabledCheckCode % { "mask" : 0xF0 }
cryptoRegRegRegInst("aese", "AESE64", "SimdAesOp",
aes_enabled, aeseCode)
cryptoRegRegRegInst("aesd", "AESD64", "SimdAesOp",
aes_enabled, aesdCode)
cryptoRegRegInst("aesmc", "AESMC64", "SimdAesMixOp",
aes_enabled, aesmcCode)
cryptoRegRegInst("aesimc", "AESIMC64", "SimdAesMixOp",
aes_enabled, aesimcCode)
sha1_enabled = cryptoEnabledCheckCode % { "mask" : 0xF00 }
cryptoRegRegRegInst("sha1c", "SHA1C64", "SimdSha1HashOp",
sha1_enabled, sha1_cCode)