stdlib: Turn off RVV for U74 core

The U74 core doesn't support vector instructions.

Change-Id: Iadfb6b43ef8c62dcad23391e468a43b908e4a22c
Signed-off-by: Hoa Nguyen <hn@hnpl.org>

src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

@@ -214,3 +214,4 @@ class U74Core(BaseCPUCore):
         core_id,
     ):
         super().__init__(core=U74CPU(cpu_id=core_id), isa=ISA.RISCV)
+        self.core.isa[0].enable_rvv = False