From dce8d07703d0a799959b7bce79c43790775b0323 Mon Sep 17 00:00:00 2001 From: Hoa Nguyen Date: Sun, 15 Oct 2023 19:42:35 -0700 Subject: [PATCH] stdlib: Turn off RVV for U74 core The U74 core doesn't support vector instructions. Change-Id: Iadfb6b43ef8c62dcad23391e468a43b908e4a22c Signed-off-by: Hoa Nguyen --- src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py index 22ec29e59d..19dc2f2e8c 100644 --- a/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py +++ b/src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py @@ -214,3 +214,4 @@ class U74Core(BaseCPUCore): core_id, ): super().__init__(core=U74CPU(cpu_id=core_id), isa=ISA.RISCV) + self.core.isa[0].enable_rvv = False