misc,python: Add isort hook to pre-commit (#431)

src/python/gem5/components/boards/abstract_board.py

@@ -24,23 +24,33 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta, abstractmethod
 import inspect
-
-from .mem_mode import MemMode, mem_mode_to_string
-from ...resources.resource import WorkloadResource
+from abc import (
+    ABCMeta,
+    abstractmethod,
+)
+from typing import (
+    List,
+    Optional,
+    Sequence,
+    Tuple,
+)
 
 from m5.objects import (
     AddrRange,
-    System,
-    Port,
-    IOXBar,
     ClockDomain,
+    IOXBar,
+    Port,
     SrcClockDomain,
+    System,
     VoltageDomain,
 )
 
-from typing import List, Optional, Sequence, Tuple
+from ...resources.resource import WorkloadResource
+from .mem_mode import (
+    MemMode,
+    mem_mode_to_string,
+)
 
 
 class AbstractBoard:

src/python/gem5/components/boards/abstract_system_board.py

@@ -26,10 +26,13 @@
 
 from abc import ABCMeta
 
-from .abstract_board import AbstractBoard
-from ...utils.override import overrides
+from m5.objects import (
+    SimObject,
+    System,
+)
 
-from m5.objects import System, SimObject
+from ...utils.override import overrides
+from .abstract_board import AbstractBoard
 
 
 class AbstractSystemBoard(System, AbstractBoard):

src/python/gem5/components/boards/arm_board.py

@@ -24,43 +24,48 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import (
-    Port,
-    IOXBar,
-    Bridge,
-    BadAddr,
-    Terminal,
-    PciVirtIO,
-    VncServer,
-    AddrRange,
-    ArmSystem,
-    ArmRelease,
-    ArmFsLinux,
-    VirtIOBlock,
-    CowDiskImage,
-    RawDiskImage,
-    VoltageDomain,
-    SrcClockDomain,
-    ArmDefaultRelease,
-    VExpress_GEM5_Base,
-    VExpress_GEM5_Foundation,
-    SimObject,
+import os
+from abc import ABCMeta
+from typing import (
+    List,
+    Sequence,
+    Tuple,
 )
 
-import os
 import m5
-from abc import ABCMeta
+from m5.objects import (
+    AddrRange,
+    ArmDefaultRelease,
+    ArmFsLinux,
+    ArmRelease,
+    ArmSystem,
+    BadAddr,
+    Bridge,
+    CowDiskImage,
+    IOXBar,
+    PciVirtIO,
+    Port,
+    RawDiskImage,
+    SimObject,
+    SrcClockDomain,
+    Terminal,
+    VExpress_GEM5_Base,
+    VExpress_GEM5_Foundation,
+    VirtIOBlock,
+    VncServer,
+    VoltageDomain,
+)
+
 from ...isas import ISA
-from ...utils.requires import requires
-from ...utils.override import overrides
-from typing import List, Sequence, Tuple
-from .abstract_board import AbstractBoard
 from ...resources.resource import AbstractResource
-from .kernel_disk_workload import KernelDiskWorkload
-from ..cachehierarchies.classic.no_cache import NoCache
-from ..processors.abstract_processor import AbstractProcessor
-from ..memory.abstract_memory_system import AbstractMemorySystem
+from ...utils.override import overrides
+from ...utils.requires import requires
 from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
+from ..cachehierarchies.classic.no_cache import NoCache
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..processors.abstract_processor import AbstractProcessor
+from .abstract_board import AbstractBoard
+from .kernel_disk_workload import KernelDiskWorkload
 
 
 class ArmBoard(ArmSystem, AbstractBoard, KernelDiskWorkload):

src/python/gem5/components/boards/experimental/lupv_board.py

@@ -27,42 +27,31 @@
 import os
 from typing import List
 
-from ....utils.override import overrides
-from ..abstract_system_board import AbstractSystemBoard
-from ...processors.abstract_processor import AbstractProcessor
-from ...memory.abstract_memory_system import AbstractMemorySystem
-from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
-from ..kernel_disk_workload import KernelDiskWorkload
-from ....resources.resource import AbstractResource
-from ....isas import ISA
-
 import m5
 from m5.objects import (
-    Bridge,
-    PMAChecker,
-    RiscvLinux,
-    RiscvRTC,
     AddrRange,
-    IOXBar,
+    Bridge,
     Clint,
-    Plic,
-    Terminal,
+    CowDiskImage,
+    Frequency,
+    IOXBar,
     LupioBLK,
     LupioIPI,
     LupioPIC,
     LupioRNG,
     LupioRTC,
+    LupioSYS,
     LupioTMR,
     LupioTTY,
-    LupioSYS,
     LupV,
-    AddrRange,
-    CowDiskImage,
-    RawDiskImage,
-    Frequency,
+    Plic,
+    PMAChecker,
     Port,
+    RawDiskImage,
+    RiscvLinux,
+    RiscvRTC,
+    Terminal,
 )
-
 from m5.util.fdthelper import (
     Fdt,
     FdtNode,
@@ -72,6 +61,15 @@ from m5.util.fdthelper import (
     FdtState,
 )
 
+from ....isas import ISA
+from ....resources.resource import AbstractResource
+from ....utils.override import overrides
+from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
+from ...memory.abstract_memory_system import AbstractMemorySystem
+from ...processors.abstract_processor import AbstractProcessor
+from ..abstract_system_board import AbstractSystemBoard
+from ..kernel_disk_workload import KernelDiskWorkload
+
 
 class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
     """

src/python/gem5/components/boards/kernel_disk_workload.py

@@ -24,22 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import os
 from abc import abstractmethod
-
-from .abstract_board import AbstractBoard
-from ...resources.resource import (
-    DiskImageResource,
-    BootloaderResource,
-    CheckpointResource,
-    KernelResource,
+from pathlib import Path
+from typing import (
+    List,
+    Optional,
+    Union,
 )
 
-from typing import List, Optional, Union
-import os
-from pathlib import Path
-
 import m5
 
+from ...resources.resource import (
+    BootloaderResource,
+    CheckpointResource,
+    DiskImageResource,
+    KernelResource,
+)
+from .abstract_board import AbstractBoard
+
 
 class KernelDiskWorkload:
     """

src/python/gem5/components/boards/riscv_board.py

@@ -26,41 +26,28 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import os
-
 from typing import List
 
-from ...utils.override import overrides
-from .abstract_system_board import AbstractSystemBoard
-from .kernel_disk_workload import KernelDiskWorkload
-from ..processors.abstract_processor import AbstractProcessor
-from ..memory.abstract_memory_system import AbstractMemorySystem
-from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
-from ...resources.resource import AbstractResource
-
-from ...isas import ISA
-
 import m5
-
 from m5.objects import (
+    AddrRange,
     BadAddr,
     Bridge,
-    PMAChecker,
-    RiscvLinux,
-    AddrRange,
-    IOXBar,
-    RiscvRTC,
-    HiFive,
-    GenericRiscvPciHost,
-    IGbE_e1000,
     CowDiskImage,
+    Frequency,
+    GenericRiscvPciHost,
+    HiFive,
+    IGbE_e1000,
+    IOXBar,
+    PMAChecker,
+    Port,
     RawDiskImage,
+    RiscvLinux,
     RiscvMmioVirtIO,
+    RiscvRTC,
     VirtIOBlock,
     VirtIORng,
-    Frequency,
-    Port,
 )
-
 from m5.util.fdthelper import (
     Fdt,
     FdtNode,
@@ -70,6 +57,15 @@ from m5.util.fdthelper import (
     FdtState,
 )
 
+from ...isas import ISA
+from ...resources.resource import AbstractResource
+from ...utils.override import overrides
+from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..processors.abstract_processor import AbstractProcessor
+from .abstract_system_board import AbstractSystemBoard
+from .kernel_disk_workload import KernelDiskWorkload
+
 
 class RiscvBoard(AbstractSystemBoard, KernelDiskWorkload):
     """

src/python/gem5/components/boards/se_binary_workload.py

@@ -24,27 +24,32 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .abstract_board import AbstractBoard
-
-from ...resources.resource import (
-    FileResource,
-    AbstractResource,
-    BinaryResource,
-    CheckpointResource,
-    SimpointResource,
-    SimpointDirectoryResource,
+from pathlib import Path
+from typing import (
+    List,
+    Optional,
+    Union,
 )
 
-from ..processors.switchable_processor import SwitchableProcessor
+from m5.objects import (
+    Process,
+    SEWorkload,
+)
+from m5.util import warn
 
 from gem5.resources.elfie import ELFieInfo
 from gem5.resources.looppoint import Looppoint
 
-from m5.objects import SEWorkload, Process
-
-from typing import Optional, List, Union
-from m5.util import warn
-from pathlib import Path
+from ...resources.resource import (
+    AbstractResource,
+    BinaryResource,
+    CheckpointResource,
+    FileResource,
+    SimpointDirectoryResource,
+    SimpointResource,
+)
+from ..processors.switchable_processor import SwitchableProcessor
+from .abstract_board import AbstractBoard
 
 
 class SEBinaryWorkload:

src/python/gem5/components/boards/simple_board.py

@@ -24,16 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import AddrRange, IOXBar, Port
+from typing import List
 
+from m5.objects import (
+    AddrRange,
+    IOXBar,
+    Port,
+)
+
+from ...utils.override import overrides
+from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..processors.abstract_processor import AbstractProcessor
 from .abstract_system_board import AbstractSystemBoard
 from .se_binary_workload import SEBinaryWorkload
-from ..processors.abstract_processor import AbstractProcessor
-from ..memory.abstract_memory_system import AbstractMemorySystem
-from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
-from ...utils.override import overrides
-
-from typing import List
 
 
 class SimpleBoard(AbstractSystemBoard, SEBinaryWorkload):

src/python/gem5/components/boards/test_board.py

@@ -24,17 +24,23 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import Port, IOXBar, AddrRange
+from typing import (
+    List,
+    Optional,
+)
+
+from m5.objects import (
+    AddrRange,
+    IOXBar,
+    Port,
+)
 
 from ...utils.override import overrides
+from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..processors.abstract_generator import AbstractGenerator
 from .abstract_board import AbstractBoard
 from .abstract_system_board import AbstractSystemBoard
-from ..processors.abstract_generator import AbstractGenerator
-from ..memory.abstract_memory_system import AbstractMemorySystem
-from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
-
-
-from typing import List, Optional
 
 
 class TestBoard(AbstractSystemBoard):

src/python/gem5/components/boards/x86_board.py

@@ -25,40 +25,41 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from .kernel_disk_workload import KernelDiskWorkload
-from ...resources.resource import AbstractResource
-from ...utils.override import overrides
-from .abstract_system_board import AbstractSystemBoard
-from ...isas import ISA
-
-from m5.objects import (
-    Pc,
-    AddrRange,
-    X86FsLinux,
-    Addr,
-    X86SMBiosBiosInformation,
-    X86IntelMPProcessor,
-    X86IntelMPIOAPIC,
-    X86IntelMPBus,
-    X86IntelMPBusHierarchy,
-    X86IntelMPIOIntAssignment,
-    X86E820Entry,
-    Bridge,
-    IOXBar,
-    IdeDisk,
-    CowDiskImage,
-    RawDiskImage,
-    BaseXBar,
-    Port,
+from typing import (
+    List,
+    Sequence,
 )
 
+from m5.objects import (
+    Addr,
+    AddrRange,
+    BaseXBar,
+    Bridge,
+    CowDiskImage,
+    IdeDisk,
+    IOXBar,
+    Pc,
+    Port,
+    RawDiskImage,
+    X86E820Entry,
+    X86FsLinux,
+    X86IntelMPBus,
+    X86IntelMPBusHierarchy,
+    X86IntelMPIOAPIC,
+    X86IntelMPIOIntAssignment,
+    X86IntelMPProcessor,
+    X86SMBiosBiosInformation,
+)
 from m5.util.convert import toMemorySize
 
-from ..processors.abstract_processor import AbstractProcessor
-from ..memory.abstract_memory_system import AbstractMemorySystem
+from ...isas import ISA
+from ...resources.resource import AbstractResource
+from ...utils.override import overrides
 from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
-
-from typing import List, Sequence
+from ..memory.abstract_memory_system import AbstractMemorySystem
+from ..processors.abstract_processor import AbstractProcessor
+from .abstract_system_board import AbstractSystemBoard
+from .kernel_disk_workload import KernelDiskWorkload
 
 
 class X86Board(AbstractSystemBoard, KernelDiskWorkload):

src/python/gem5/components/cachehierarchies/abstract_cache_hierarchy.py

@@ -24,12 +24,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta, abstractmethod
-
-from ..boards.abstract_board import AbstractBoard
+from abc import (
+    ABCMeta,
+    abstractmethod,
+)
 
 from m5.objects import SubSystem
 
+from ..boards.abstract_board import AbstractBoard
+
 
 class AbstractCacheHierarchy(SubSystem):
     __metaclass__ = ABCMeta

src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py

@@ -24,14 +24,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import abstractmethod
-from gem5.isas import ISA
-from gem5.components.processors.cpu_types import CPUTypes
-from gem5.components.processors.abstract_core import AbstractCore
-
-from m5.objects import Cache_Controller, MessageBuffer, RubyNetwork
-
 import math
+from abc import abstractmethod
+
+from m5.objects import (
+    Cache_Controller,
+    MessageBuffer,
+    RubyNetwork,
+)
+
+from gem5.components.processors.abstract_core import AbstractCore
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.isas import ISA
 
 
 class TriggerMessageBuffer(MessageBuffer):

src/python/gem5/components/cachehierarchies/chi/nodes/directory.py

@@ -24,9 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .abstract_node import AbstractNode
+from m5.objects import (
+    NULL,
+    ClockDomain,
+    RubyCache,
+    RubyNetwork,
+)
 
-from m5.objects import ClockDomain, NULL, RubyCache, RubyNetwork
+from .abstract_node import AbstractNode
 
 
 class SimpleDirectory(AbstractNode):

src/python/gem5/components/cachehierarchies/chi/nodes/dma_requestor.py

@@ -24,13 +24,16 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    ClockDomain,
+    RubyCache,
+)
+
 from gem5.components.processors.abstract_core import AbstractCore
 from gem5.isas import ISA
 
 from .abstract_node import AbstractNode
 
-from m5.objects import ClockDomain, RubyCache
-
 
 class DMARequestor(AbstractNode):
     def __init__(self, network, cache_line_size, clk_domain: ClockDomain):

src/python/gem5/components/cachehierarchies/chi/nodes/private_l1_moesi_cache.py

@@ -24,13 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    ClockDomain,
+    RubyCache,
+    RubyNetwork,
+)
+
 from gem5.components.processors.abstract_core import AbstractCore
 from gem5.isas import ISA
 
 from .abstract_node import AbstractNode
 
-from m5.objects import ClockDomain, RubyCache, RubyNetwork
-
 
 class PrivateL1MOESICache(AbstractNode):
     def __init__(

src/python/gem5/components/cachehierarchies/chi/private_l1_cache_hierarchy.py

@@ -27,30 +27,34 @@
 from itertools import chain
 from typing import List
 
-from m5.objects.SubSystem import SubSystem
-from gem5.components.cachehierarchies.ruby.abstract_ruby_cache_hierarchy import (
-    AbstractRubyCacheHierarchy,
+from m5.objects import (
+    NULL,
+    RubyPortProxy,
+    RubySequencer,
+    RubySystem,
 )
+from m5.objects.SubSystem import SubSystem
+
+from gem5.coherence_protocol import CoherenceProtocol
+from gem5.components.boards.abstract_board import AbstractBoard
 from gem5.components.cachehierarchies.abstract_cache_hierarchy import (
     AbstractCacheHierarchy,
 )
-from gem5.coherence_protocol import CoherenceProtocol
-from gem5.isas import ISA
-from gem5.utils.requires import requires
-from gem5.utils.override import overrides
-from gem5.components.boards.abstract_board import AbstractBoard
-from gem5.components.processors.abstract_core import AbstractCore
-
+from gem5.components.cachehierarchies.ruby.abstract_ruby_cache_hierarchy import (
+    AbstractRubyCacheHierarchy,
+)
 from gem5.components.cachehierarchies.ruby.topologies.simple_pt2pt import (
     SimplePt2Pt,
 )
+from gem5.components.processors.abstract_core import AbstractCore
+from gem5.isas import ISA
+from gem5.utils.override import overrides
+from gem5.utils.requires import requires
 
-from .nodes.private_l1_moesi_cache import PrivateL1MOESICache
-from .nodes.dma_requestor import DMARequestor
 from .nodes.directory import SimpleDirectory
+from .nodes.dma_requestor import DMARequestor
 from .nodes.memory_controller import MemoryController
-
-from m5.objects import NULL, RubySystem, RubySequencer, RubyPortProxy
+from .nodes.private_l1_moesi_cache import PrivateL1MOESICache
 
 
 class PrivateL1CacheHierarchy(AbstractRubyCacheHierarchy):

src/python/gem5/components/cachehierarchies/classic/abstract_classic_cache_hierarchy.py

@@ -25,11 +25,12 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from abc import abstractmethod
-from ....utils.override import overrides
-from ..abstract_cache_hierarchy import AbstractCacheHierarchy
 
 from m5.objects import Port
 
+from ....utils.override import overrides
+from ..abstract_cache_hierarchy import AbstractCacheHierarchy
+
 
 class AbstractClassicCacheHierarchy(AbstractCacheHierarchy):
     """

src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py

@@ -24,12 +24,16 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....utils.override import *
-
-from m5.objects import Cache, BasePrefetcher, StridePrefetcher
-
 from typing import Type
 
+from m5.objects import (
+    BasePrefetcher,
+    Cache,
+    StridePrefetcher,
+)
+
+from .....utils.override import *
+
 
 class L1DCache(Cache):
     """

src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py

@@ -26,7 +26,11 @@
 
 from typing import Type
 
-from m5.objects import Cache, BasePrefetcher, StridePrefetcher
+from m5.objects import (
+    BasePrefetcher,
+    Cache,
+    StridePrefetcher,
+)
 
 from .....utils.override import *
 

src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py

@@ -24,12 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....utils.override import *
-
-from m5.objects import Cache, Clusivity, BasePrefetcher, StridePrefetcher
-
 from typing import Type
 
+from m5.objects import (
+    BasePrefetcher,
+    Cache,
+    Clusivity,
+    StridePrefetcher,
+)
+
+from .....utils.override import *
+
 
 class L2Cache(Cache):
     """

src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py

@@ -24,9 +24,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....utils.override import *
+from m5.objects import (
+    BasePrefetcher,
+    Cache,
+    StridePrefetcher,
+)
 
-from m5.objects import Cache, BasePrefetcher, StridePrefetcher
+from .....utils.override import *
 
 
 class MMUCache(Cache):

src/python/gem5/components/cachehierarchies/classic/no_cache.py

@@ -24,14 +24,19 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
-from ..abstract_cache_hierarchy import AbstractCacheHierarchy
-from ...boards.abstract_board import AbstractBoard
+from m5.objects import (
+    BadAddr,
+    BaseXBar,
+    Bridge,
+    Port,
+    SystemXBar,
+)
+
 from ....isas import ISA
-
-from m5.objects import Bridge, BaseXBar, SystemXBar, BadAddr, Port
-
 from ....utils.override import *
+from ...boards.abstract_board import AbstractBoard
+from ..abstract_cache_hierarchy import AbstractCacheHierarchy
+from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 
 
 class NoCache(AbstractClassicCacheHierarchy):

src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py

@@ -24,17 +24,22 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    BadAddr,
+    BaseXBar,
+    Cache,
+    Port,
+    SystemXBar,
+)
+
+from ....isas import ISA
+from ....utils.override import *
+from ...boards.abstract_board import AbstractBoard
 from ..abstract_cache_hierarchy import AbstractCacheHierarchy
 from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.mmu_cache import MMUCache
-from ...boards.abstract_board import AbstractBoard
-from ....isas import ISA
-
-from m5.objects import Cache, BaseXBar, SystemXBar, BadAddr, Port
-
-from ....utils.override import *
 
 
 class PrivateL1CacheHierarchy(AbstractClassicCacheHierarchy):

src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py

@@ -24,18 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    BadAddr,
+    BaseXBar,
+    Cache,
+    L2XBar,
+    Port,
+    SystemXBar,
+)
+
+from ....isas import ISA
+from ....utils.override import *
+from ...boards.abstract_board import AbstractBoard
 from ..abstract_cache_hierarchy import AbstractCacheHierarchy
-from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy
+from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.l2cache import L2Cache
 from .caches.mmu_cache import MMUCache
-from ...boards.abstract_board import AbstractBoard
-from ....isas import ISA
-from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
-
-from ....utils.override import *
 
 
 class PrivateL1PrivateL2CacheHierarchy(

src/python/gem5/components/cachehierarchies/classic/private_l1_shared_l2_cache_hierarchy.py

@@ -24,18 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    BadAddr,
+    BaseXBar,
+    Cache,
+    L2XBar,
+    Port,
+    SystemXBar,
+)
+
+from ....isas import ISA
+from ....utils.override import *
+from ...boards.abstract_board import AbstractBoard
 from ..abstract_cache_hierarchy import AbstractCacheHierarchy
-from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy
+from .abstract_classic_cache_hierarchy import AbstractClassicCacheHierarchy
 from .caches.l1dcache import L1DCache
 from .caches.l1icache import L1ICache
 from .caches.l2cache import L2Cache
 from .caches.mmu_cache import MMUCache
-from ...boards.abstract_board import AbstractBoard
-from ....isas import ISA
-from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
-
-from ....utils.override import *
 
 
 class PrivateL1SharedL2CacheHierarchy(

src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py

@@ -24,14 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import math
 from abc import abstractmethod
-from .....isas import ISA
-from ....processors.cpu_types import CPUTypes
-from ....processors.abstract_core import AbstractCore
 
 from m5.objects import L1Cache_Controller
 
-import math
+from .....isas import ISA
+from ....processors.abstract_core import AbstractCore
+from ....processors.cpu_types import CPUTypes
 
 
 class AbstractL1Cache(L1Cache_Controller):

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/directory.py

@@ -24,11 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    MessageBuffer,
+    RubyDirectoryMemory,
+)
+
 from ......utils.override import overrides
 from ..abstract_directory import AbstractDirectory
 
-from m5.objects import MessageBuffer, RubyDirectoryMemory
-
 
 class Directory(AbstractDirectory):
     def __init__(self, network, cache_line_size, mem_range, port):

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/dma_controller.py

@@ -24,9 +24,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ......utils.override import overrides
+from m5.objects import (
+    DMA_Controller,
+    MessageBuffer,
+)
 
-from m5.objects import MessageBuffer, DMA_Controller
+from ......utils.override import overrides
 
 
 class DMAController(DMA_Controller):

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l1_cache.py

@@ -24,20 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....processors.abstract_core import AbstractCore
-from ......isas import ISA
-from ......utils.override import *
+import math
 
 from m5.objects import (
-    MessageBuffer,
-    RubyPrefetcher,
-    RubyCache,
-    ClockDomain,
     LRURP,
+    ClockDomain,
     L0Cache_Controller,
+    MessageBuffer,
+    RubyCache,
+    RubyPrefetcher,
 )
 
-import math
+from ......isas import ISA
+from ......utils.override import *
+from .....processors.abstract_core import AbstractCore
 
 
 # L0Cache_Controller is the ruby backend's terminology corresponding to

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l2_cache.py

@@ -24,19 +24,19 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....processors.abstract_core import AbstractCore
-from ......isas import ISA
-from ......utils.override import *
+import math
 
 from m5.objects import (
-    MessageBuffer,
-    RubyPrefetcher,
-    RubyCache,
     ClockDomain,
     L1Cache_Controller,
+    MessageBuffer,
+    RubyCache,
+    RubyPrefetcher,
 )
 
-import math
+from ......isas import ISA
+from ......utils.override import *
+from .....processors.abstract_core import AbstractCore
 
 
 # L1Cache_Controller is ruby backend's terminology corresponding to

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_three_level/l3_cache.py

@@ -24,10 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import MessageBuffer, RubyCache, L2Cache_Controller
-
 import math
 
+from m5.objects import (
+    L2Cache_Controller,
+    MessageBuffer,
+    RubyCache,
+)
+
 
 # L2Cache_Controller is ruby backend's terminology corresponding to
 # L3 cache in stdlib.

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py

@@ -24,11 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    MessageBuffer,
+    RubyDirectoryMemory,
+)
+
 from ......utils.override import overrides
 from ..abstract_directory import AbstractDirectory
 
-from m5.objects import MessageBuffer, RubyDirectoryMemory
-
 
 class Directory(AbstractDirectory):
     def __init__(self, network, cache_line_size, mem_range, port):

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py

@@ -24,11 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import MessageBuffer
+
 from ......utils.override import overrides
 from ..abstract_dma_controller import AbstractDMAController
 
-from m5.objects import MessageBuffer
-
 
 class DMAController(AbstractDMAController):
     def __init__(self, network, cache_line_size):

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py

@@ -24,15 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .....processors.abstract_core import AbstractCore
-from ......isas import ISA
-from ..abstract_l1_cache import AbstractL1Cache
-from ......utils.override import *
-
-from m5.objects import MessageBuffer, RubyPrefetcher, RubyCache, ClockDomain
-
 import math
 
+from m5.objects import (
+    ClockDomain,
+    MessageBuffer,
+    RubyCache,
+    RubyPrefetcher,
+)
+
+from ......isas import ISA
+from ......utils.override import *
+from .....processors.abstract_core import AbstractCore
+from ..abstract_l1_cache import AbstractL1Cache
+
 
 class L1Cache(AbstractL1Cache):
     def __init__(

src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py

@@ -24,13 +24,16 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ..abstract_l2_cache import AbstractL2Cache
-from ......utils.override import *
-
-from m5.objects import MessageBuffer, RubyCache
-
 import math
 
+from m5.objects import (
+    MessageBuffer,
+    RubyCache,
+)
+
+from ......utils.override import *
+from ..abstract_l2_cache import AbstractL2Cache
+
 
 class L2Cache(AbstractL2Cache):
     def __init__(

src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py

@@ -24,11 +24,13 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ..abstract_directory import AbstractDirectory
+from m5.objects import (
+    MessageBuffer,
+    RubyDirectoryMemory,
+)
+
 from ......utils.override import overrides
-
-
-from m5.objects import MessageBuffer, RubyDirectoryMemory
+from ..abstract_directory import AbstractDirectory
 
 
 class Directory(AbstractDirectory):

src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py

@@ -24,11 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ..abstract_dma_controller import AbstractDMAController
-from ......utils.override import overrides
-
 from m5.objects import MessageBuffer
 
+from ......utils.override import overrides
+from ..abstract_dma_controller import AbstractDMAController
+
 
 class DMAController(AbstractDMAController):
     """

src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py

@@ -24,13 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import (
+    ClockDomain,
+    MessageBuffer,
+    RubyCache,
+)
+
+from ......isas import ISA
 from ......utils.override import overrides
 from .....processors.abstract_core import AbstractCore
-from ......isas import ISA
 from ..abstract_l1_cache import AbstractL1Cache
 
-from m5.objects import MessageBuffer, RubyCache, ClockDomain
-
 
 class L1Cache(AbstractL1Cache):
     def __init__(

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/core_complex.py

@@ -24,11 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import List, Tuple
+from typing import (
+    List,
+    Tuple,
+)
+
+from m5.objects import (
+    RubySequencer,
+    SubSystem,
+)
 
-from gem5.isas import ISA
 from gem5.components.boards.abstract_board import AbstractBoard
-from gem5.components.processors.abstract_core import AbstractCore
 from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l1_cache import (
     L1Cache,
 )
@@ -38,14 +44,14 @@ from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l2_cache impo
 from gem5.components.cachehierarchies.ruby.caches.mesi_three_level.l3_cache import (
     L3Cache,
 )
-
-from m5.objects import SubSystem, RubySequencer
+from gem5.components.processors.abstract_core import AbstractCore
+from gem5.isas import ISA
 
 from .ruby_network_components import (
-    RubyRouter,
     RubyExtLink,
     RubyIntLink,
     RubyNetworkComponent,
+    RubyRouter,
 )
 
 

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi.py

@@ -24,26 +24,32 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
-from ....abstract_three_level_cache_hierarchy import (
-    AbstractThreeLevelCacheHierarchy,
+from m5.objects import (
+    DMASequencer,
+    RubyPortProxy,
+    RubySystem,
 )
+
 from ......coherence_protocol import CoherenceProtocol
 from ......components.boards.abstract_board import AbstractBoard
-from ......utils.requires import requires
-
 from ......components.cachehierarchies.ruby.caches.mesi_three_level.directory import (
     Directory,
 )
 from ......components.cachehierarchies.ruby.caches.mesi_three_level.dma_controller import (
     DMAController,
 )
-
-from m5.objects import RubySystem, DMASequencer, RubyPortProxy
-
+from ......utils.requires import requires
+from ....abstract_three_level_cache_hierarchy import (
+    AbstractThreeLevelCacheHierarchy,
+)
+from ...abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
 from .core_complex import CoreComplex
 from .octopi_network import OctopiNetwork
-from .ruby_network_components import RubyRouter, RubyExtLink, RubyIntLink
+from .ruby_network_components import (
+    RubyExtLink,
+    RubyIntLink,
+    RubyRouter,
+)
 
 
 # CoreComplex sub-systems own the L1, L2, L3 controllers

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/octopi_network.py

@@ -27,9 +27,9 @@
 from m5.objects import SimpleNetwork
 
 from .ruby_network_components import (
+    RubyIntLink,
     RubyNetworkComponent,
     RubyRouter,
-    RubyIntLink,
 )
 
 

src/python/gem5/components/cachehierarchies/ruby/caches/prebuilt/octopi_cache/ruby_network_components.py

@@ -24,7 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import Switch, SimpleIntLink, SimpleExtLink
+from m5.objects import (
+    SimpleExtLink,
+    SimpleIntLink,
+    Switch,
+)
 
 
 class RubyNetworkComponent:

src/python/gem5/components/cachehierarchies/ruby/mesi_three_level_cache_hierarchy.py

@@ -25,23 +25,27 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
+from m5.objects import (
+    DMASequencer,
+    RubyPortProxy,
+    RubySequencer,
+    RubySystem,
+)
+
+from ....coherence_protocol import CoherenceProtocol
+from ....isas import ISA
+from ....utils.requires import requires
+from ...boards.abstract_board import AbstractBoard
 from ..abstract_three_level_cache_hierarchy import (
     AbstractThreeLevelCacheHierarchy,
 )
-from ....coherence_protocol import CoherenceProtocol
-from ....isas import ISA
-from ...boards.abstract_board import AbstractBoard
-from ....utils.requires import requires
-
-from .topologies.simple_pt2pt import SimplePt2Pt
+from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
+from .caches.mesi_three_level.directory import Directory
+from .caches.mesi_three_level.dma_controller import DMAController
 from .caches.mesi_three_level.l1_cache import L1Cache
 from .caches.mesi_three_level.l2_cache import L2Cache
 from .caches.mesi_three_level.l3_cache import L3Cache
-from .caches.mesi_three_level.directory import Directory
-from .caches.mesi_three_level.dma_controller import DMAController
-
-from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy
+from .topologies.simple_pt2pt import SimplePt2Pt
 
 
 class MESIThreeLevelCacheHierarchy(

src/python/gem5/components/cachehierarchies/ruby/mesi_two_level_cache_hierarchy.py

@@ -25,20 +25,24 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
-from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy
+from m5.objects import (
+    DMASequencer,
+    RubyPortProxy,
+    RubySequencer,
+    RubySystem,
+)
+
 from ....coherence_protocol import CoherenceProtocol
 from ....isas import ISA
-from ...boards.abstract_board import AbstractBoard
 from ....utils.requires import requires
-
-from .topologies.simple_pt2pt import SimplePt2Pt
-from .caches.mesi_two_level.l1_cache import L1Cache
-from .caches.mesi_two_level.l2_cache import L2Cache
+from ...boards.abstract_board import AbstractBoard
+from ..abstract_two_level_cache_hierarchy import AbstractTwoLevelCacheHierarchy
+from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
 from .caches.mesi_two_level.directory import Directory
 from .caches.mesi_two_level.dma_controller import DMAController
-
-from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy
+from .caches.mesi_two_level.l1_cache import L1Cache
+from .caches.mesi_two_level.l2_cache import L2Cache
+from .topologies.simple_pt2pt import SimplePt2Pt
 
 
 class MESITwoLevelCacheHierarchy(

src/python/gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py

@@ -24,20 +24,24 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .caches.mi_example.l1_cache import L1Cache
-from .caches.mi_example.dma_controller import DMAController
-from .caches.mi_example.directory import Directory
-from .topologies.simple_pt2pt import SimplePt2Pt
-from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
-from ..abstract_cache_hierarchy import AbstractCacheHierarchy
-from ...boards.abstract_board import AbstractBoard
+from m5.objects import (
+    DMASequencer,
+    RubyPortProxy,
+    RubySequencer,
+    RubySystem,
+)
+
 from ....coherence_protocol import CoherenceProtocol
 from ....isas import ISA
 from ....utils.override import overrides
 from ....utils.requires import requires
-
-
-from m5.objects import RubySystem, RubySequencer, DMASequencer, RubyPortProxy
+from ...boards.abstract_board import AbstractBoard
+from ..abstract_cache_hierarchy import AbstractCacheHierarchy
+from .abstract_ruby_cache_hierarchy import AbstractRubyCacheHierarchy
+from .caches.mi_example.directory import Directory
+from .caches.mi_example.dma_controller import DMAController
+from .caches.mi_example.l1_cache import L1Cache
+from .topologies.simple_pt2pt import SimplePt2Pt
 
 
 class MIExampleCacheHierarchy(AbstractRubyCacheHierarchy):

src/python/gem5/components/cachehierarchies/ruby/topologies/simple_pt2pt.py

@@ -24,7 +24,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.objects import SimpleNetwork, Switch, SimpleExtLink, SimpleIntLink
+from m5.objects import (
+    SimpleExtLink,
+    SimpleIntLink,
+    SimpleNetwork,
+    Switch,
+)
 
 
 class SimplePt2Pt(SimpleNetwork):

src/python/gem5/components/memory/__init__.py

@@ -24,26 +24,32 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .single_channel import SingleChannelDDR3_1600
-from .single_channel import SingleChannelDDR3_2133
-from .single_channel import SingleChannelDDR4_2400
-from .single_channel import SingleChannelHBM
-from .single_channel import SingleChannelLPDDR3_1600
-from .single_channel import DIMM_DDR5_4400
-from .single_channel import DIMM_DDR5_6400
-from .single_channel import DIMM_DDR5_8400
-from .multi_channel import DualChannelDDR3_1600
-from .multi_channel import DualChannelDDR3_2133
-from .multi_channel import DualChannelDDR4_2400
-from .multi_channel import DualChannelLPDDR3_1600
 from .hbm import HBM2Stack
+from .multi_channel import (
+    DualChannelDDR3_1600,
+    DualChannelDDR3_2133,
+    DualChannelDDR4_2400,
+    DualChannelLPDDR3_1600,
+)
+from .single_channel import (
+    DIMM_DDR5_4400,
+    DIMM_DDR5_6400,
+    DIMM_DDR5_8400,
+    SingleChannelDDR3_1600,
+    SingleChannelDDR3_2133,
+    SingleChannelDDR4_2400,
+    SingleChannelHBM,
+    SingleChannelLPDDR3_1600,
+)
 
 try:
-    from .dramsys import DRAMSysMem
-    from .dramsys import DRAMSysDDR4_1866
-    from .dramsys import DRAMSysDDR3_1600
-    from .dramsys import DRAMSysLPDDR4_3200
-    from .dramsys import DRAMSysHBM2
+    from .dramsys import (
+        DRAMSysDDR3_1600,
+        DRAMSysDDR4_1866,
+        DRAMSysHBM2,
+        DRAMSysLPDDR4_3200,
+        DRAMSysMem,
+    )
 except:
     # In the case that DRAMSys is not compiled into the gem5 binary, importing
     # DRAMSys components will fail. This try-exception statement is needed to

src/python/gem5/components/memory/abstract_memory_system.py

@@ -24,14 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta, abstractmethod
-from typing import Tuple, Sequence, List
+from abc import (
+    ABCMeta,
+    abstractmethod,
+)
+from typing import (
+    List,
+    Sequence,
+    Tuple,
+)
 
+from m5.objects import (
+    AddrRange,
+    MemCtrl,
+    Port,
+    SubSystem,
+)
 
 from ..boards.abstract_board import AbstractBoard
 
-from m5.objects import AddrRange, Port, SubSystem, MemCtrl
-
 
 class AbstractMemorySystem(SubSystem):
     __metaclass__ = ABCMeta

src/python/gem5/components/memory/dramsim_3.py

@@ -1,8 +1,19 @@
-import m5
-import os
 import configparser
+import os
+from typing import (
+    List,
+    Optional,
+    Sequence,
+    Tuple,
+)
 
-from m5.objects import DRAMsim3, AddrRange, Port, MemCtrl
+import m5
+from m5.objects import (
+    AddrRange,
+    DRAMsim3,
+    MemCtrl,
+    Port,
+)
 from m5.util.convert import toMemorySize
 
 from ...utils.override import overrides
@@ -10,9 +21,6 @@ from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
 
 
-from typing import Optional, Tuple, Sequence, List
-
-
 def config_ds3(mem_type: str, num_chnls: int) -> Tuple[str, str]:
     """
     This function creates a config file that will be used to create a memory

src/python/gem5/components/memory/dramsys.py

@@ -24,15 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Tuple, Sequence, List, Optional
 from pathlib import Path
+from typing import (
+    List,
+    Optional,
+    Sequence,
+    Tuple,
+)
 
 from m5.objects import (
-    DRAMSys,
     AddrRange,
-    Port,
-    MemCtrl,
+    DRAMSys,
     Gem5ToTlmBridge32,
+    MemCtrl,
+    Port,
     SystemC_Kernel,
 )
 from m5.util.convert import toMemorySize
@@ -41,7 +46,6 @@ from ...utils.override import overrides
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
 
-
 DEFAULT_DRAMSYS_DIRECTORY = Path("ext/dramsys/DRAMSys")
 
 

src/python/gem5/components/memory/hbm.py

@@ -27,14 +27,29 @@
 """ HBM2 memory system using HBMCtrl
 """
 
-from .memory import ChanneledMemory
-from .abstract_memory_system import AbstractMemorySystem
 from math import log
+from typing import (
+    Optional,
+    Sequence,
+    Tuple,
+    Type,
+    Union,
+)
+
+from m5.objects import (
+    AddrRange,
+    DRAMInterface,
+    HBMCtrl,
+    Port,
+)
+
 from ...utils.override import overrides
-from m5.objects import AddrRange, DRAMInterface, HBMCtrl, Port
-from typing import Type, Optional, Union, Sequence, Tuple
-from .memory import _try_convert
+from .abstract_memory_system import AbstractMemorySystem
 from .dram_interfaces.hbm import HBM_2000_4H_1x64
+from .memory import (
+    ChanneledMemory,
+    _try_convert,
+)
 
 
 class HighBandwidthMemory(ChanneledMemory):

src/python/gem5/components/memory/memory.py

@@ -28,12 +28,26 @@
 """
 
 from math import log
-from ...utils.override import overrides
+from typing import (
+    List,
+    Optional,
+    Sequence,
+    Tuple,
+    Type,
+    Union,
+)
+
+from m5.objects import (
+    AddrRange,
+    DRAMInterface,
+    MemCtrl,
+    Port,
+)
 from m5.util.convert import toMemorySize
+
+from ...utils.override import overrides
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
-from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
-from typing import Type, Sequence, Tuple, List, Optional, Union
 
 
 def _try_convert(val, cls):

src/python/gem5/components/memory/multi_channel.py

@@ -24,14 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .memory import ChanneledMemory
-from .abstract_memory_system import AbstractMemorySystem
-
 from typing import Optional
-from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
+
+from .abstract_memory_system import AbstractMemorySystem
+from .dram_interfaces.ddr3 import (
+    DDR3_1600_8x8,
+    DDR3_2133_8x8,
+)
 from .dram_interfaces.ddr4 import DDR4_2400_8x8
-from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
 from .dram_interfaces.hbm import HBM_1000_4H_1x64
+from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
+from .memory import ChanneledMemory
 
 
 def DualChannelDDR3_1600(

src/python/gem5/components/memory/simple.py

@@ -27,12 +27,23 @@
 """Simple memory controllers
 """
 
-from ...utils.override import overrides
+from typing import (
+    List,
+    Sequence,
+    Tuple,
+)
+
+from m5.objects import (
+    AddrRange,
+    MemCtrl,
+    Port,
+    SimpleMemory,
+)
 from m5.util.convert import toMemorySize
-from typing import List, Sequence, Tuple
+
+from ...utils.override import overrides
 from ..boards.abstract_board import AbstractBoard
 from .abstract_memory_system import AbstractMemorySystem
-from m5.objects import AddrRange, MemCtrl, Port, SimpleMemory
 
 
 class SingleChannelSimpleMemory(AbstractMemorySystem):

src/python/gem5/components/memory/single_channel.py

@@ -24,16 +24,22 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .memory import ChanneledMemory
-from .abstract_memory_system import AbstractMemorySystem
-
 from typing import Optional
 
-from .dram_interfaces.ddr5 import DDR5_4400_4x8, DDR5_6400_4x8, DDR5_8400_4x8
+from .abstract_memory_system import AbstractMemorySystem
+from .dram_interfaces.ddr3 import (
+    DDR3_1600_8x8,
+    DDR3_2133_8x8,
+)
 from .dram_interfaces.ddr4 import DDR4_2400_8x8
+from .dram_interfaces.ddr5 import (
+    DDR5_4400_4x8,
+    DDR5_6400_4x8,
+    DDR5_8400_4x8,
+)
 from .dram_interfaces.hbm import HBM_1000_4H_1x128
 from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
-from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
+from .memory import ChanneledMemory
 
 
 def SingleChannelDDR3_1600(

src/python/gem5/components/processors/abstract_core.py

@@ -24,14 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta, abstractmethod
-from typing import Optional, List
+from abc import (
+    ABCMeta,
+    abstractmethod,
+)
+from typing import (
+    List,
+    Optional,
+)
+
+from m5.objects import (
+    BaseMMU,
+    PcCountTrackerManager,
+    Port,
+    SubSystem,
+)
+from m5.params import PcCountPair
 
 from ...isas import ISA
 
-from m5.objects import BaseMMU, Port, SubSystem, PcCountTrackerManager
-from m5.params import PcCountPair
-
 
 class AbstractCore(SubSystem):
     __metaclass__ = ABCMeta

src/python/gem5/components/processors/abstract_generator.py

@@ -25,14 +25,13 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from abc import abstractmethod
+from typing import List
+
 from ...utils.override import overrides
+from ..boards.abstract_board import AbstractBoard
 from ..boards.mem_mode import MemMode
 from .abstract_generator_core import AbstractGeneratorCore
-
 from .abstract_processor import AbstractProcessor
-from ..boards.abstract_board import AbstractBoard
-
-from typing import List
 
 
 def partition_range(

src/python/gem5/components/processors/abstract_generator_core.py

@@ -26,14 +26,17 @@
 
 
 from abc import abstractmethod
-from m5.objects import Port, PortTerminator
-from ...utils.override import overrides
-
-from .abstract_core import AbstractCore
-from ...isas import ISA
-
 from typing import Optional
 
+from m5.objects import (
+    Port,
+    PortTerminator,
+)
+
+from ...isas import ISA
+from ...utils.override import overrides
+from .abstract_core import AbstractCore
+
 
 class AbstractGeneratorCore(AbstractCore):
     """The abstract generator core

src/python/gem5/components/processors/abstract_processor.py

@@ -24,17 +24,21 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta, abstractmethod
-
-from ...utils.requires import requires
-from .abstract_core import AbstractCore
+from abc import (
+    ABCMeta,
+    abstractmethod,
+)
+from typing import (
+    List,
+    Optional,
+)
 
 from m5.objects import SubSystem
 
-from ..boards.abstract_board import AbstractBoard
 from ...isas import ISA
-
-from typing import List, Optional
+from ...utils.requires import requires
+from ..boards.abstract_board import AbstractBoard
+from .abstract_core import AbstractCore
 
 
 class AbstractProcessor(SubSystem):

src/python/gem5/components/processors/base_cpu_core.py

@@ -24,24 +24,26 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Optional, List
-from ...utils.requires import requires
-from .abstract_core import AbstractCore
+from typing import (
+    List,
+    Optional,
+)
+
+from m5.objects import (
+    BaseCPU,
+    BaseMMU,
+    PcCountTracker,
+    PcCountTrackerManager,
+    Port,
+    Process,
+)
+from m5.params import PcCountPair
 
 from ...isas import ISA
 from ...runtime import get_runtime_isa
 from ...utils.override import overrides
 from ...utils.requires import requires
-
-from m5.objects import (
-    BaseMMU,
-    Port,
-    BaseCPU,
-    Process,
-    PcCountTracker,
-    PcCountTrackerManager,
-)
-from m5.params import PcCountPair
+from .abstract_core import AbstractCore
 
 
 class BaseCPUCore(AbstractCore):

src/python/gem5/components/processors/base_cpu_processor.py

@@ -25,23 +25,22 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from .base_cpu_core import BaseCPUCore
-from ..boards.mem_mode import MemMode
-from ...utils.override import overrides
-from ..boards.mem_mode import MemMode
-from .abstract_processor import AbstractProcessor
-from ..boards.abstract_board import AbstractBoard
-
 from typing import List
 
-from m5.util import warn
 from m5.objects import (
-    BaseO3CPU,
-    BaseMinorCPU,
     BaseAtomicSimpleCPU,
+    BaseMinorCPU,
     BaseNonCachingSimpleCPU,
+    BaseO3CPU,
     BaseTimingSimpleCPU,
 )
+from m5.util import warn
+
+from ...utils.override import overrides
+from ..boards.abstract_board import AbstractBoard
+from ..boards.mem_mode import MemMode
+from .abstract_processor import AbstractProcessor
+from .base_cpu_core import BaseCPUCore
 
 
 class BaseCPUProcessor(AbstractProcessor):

src/python/gem5/components/processors/complex_generator.py

@@ -24,12 +24,18 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ...utils.override import overrides
-from .complex_generator_core import ComplexGeneratorCore
-from .abstract_generator import AbstractGenerator
-from .abstract_generator import partition_range
+from typing import (
+    Any,
+    Iterator,
+    List,
+)
 
-from typing import Iterator, List, Any
+from ...utils.override import overrides
+from .abstract_generator import (
+    AbstractGenerator,
+    partition_range,
+)
+from .complex_generator_core import ComplexGeneratorCore
 
 
 class ComplexGenerator(AbstractGenerator):

src/python/gem5/components/processors/complex_generator_core.py

@@ -24,17 +24,25 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Iterator, Any
-from m5.ticks import fromSeconds
-from m5.util.convert import toLatency, toMemoryBandwidth
-from m5.objects import PyTrafficGen, Port
+from enum import Enum
+from typing import (
+    Any,
+    Iterator,
+)
 
-from .abstract_core import AbstractCore
-from .abstract_generator_core import AbstractGeneratorCore
+from m5.objects import (
+    Port,
+    PyTrafficGen,
+)
+from m5.ticks import fromSeconds
+from m5.util.convert import (
+    toLatency,
+    toMemoryBandwidth,
+)
 
 from ...utils.override import overrides
-
-from enum import Enum
+from .abstract_core import AbstractCore
+from .abstract_generator_core import AbstractGeneratorCore
 
 
 class TrafficModes(Enum):

src/python/gem5/components/processors/cpu_types.py

@@ -24,11 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ..boards.mem_mode import MemMode
-
+import os
 from enum import Enum
 from typing import Set
-import os
+
+from ..boards.mem_mode import MemMode
 
 
 class CPUTypes(Enum):

src/python/gem5/components/processors/gups_generator.py

@@ -28,8 +28,8 @@
 from typing import Optional
 
 from m5.objects import Addr
-from ...utils.override import overrides
 
+from ...utils.override import overrides
 from .abstract_generator import AbstractGenerator
 from .gups_generator_core import GUPSGeneratorCore
 

src/python/gem5/components/processors/gups_generator_core.py

@@ -26,10 +26,18 @@
 
 
 from typing import Optional
+
+from m5.objects import (
+    Addr,
+    GUPSGen,
+    Port,
+    SrcClockDomain,
+    VoltageDomain,
+)
+
 from ...utils.override import overrides
 from .abstract_core import AbstractCore
 from .abstract_generator_core import AbstractGeneratorCore
-from m5.objects import Port, GUPSGen, Addr, SrcClockDomain, VoltageDomain
 
 
 class GUPSGeneratorCore(AbstractGeneratorCore):

src/python/gem5/components/processors/gups_generator_ep.py

@@ -26,9 +26,11 @@
 
 
 from typing import Optional
+
 from m5.objects import Addr
-from ...utils.override import overrides
 from m5.util.convert import toMemorySize
+
+from ...utils.override import overrides
 from .abstract_generator import AbstractGenerator
 from .gups_generator_core import GUPSGeneratorCore
 

src/python/gem5/components/processors/gups_generator_par.py

@@ -26,12 +26,13 @@
 
 
 from typing import Optional
-from m5.objects import Addr
-from ...utils.override import overrides
 
+from m5.objects import Addr
+
+from ...utils.override import overrides
+from ..boards.abstract_board import AbstractBoard
 from ..boards.mem_mode import MemMode
 from .abstract_generator import AbstractGenerator
-from ..boards.abstract_board import AbstractBoard
 from .gups_generator_core import GUPSGeneratorCore
 
 

src/python/gem5/components/processors/linear_generator.py

@@ -24,13 +24,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ...utils.override import overrides
-from .linear_generator_core import LinearGeneratorCore
-from .abstract_generator import AbstractGenerator
-from .abstract_generator import partition_range
-
 from typing import List
 
+from ...utils.override import overrides
+from .abstract_generator import (
+    AbstractGenerator,
+    partition_range,
+)
+from .linear_generator_core import LinearGeneratorCore
+
 
 class LinearGenerator(AbstractGenerator):
     def __init__(

src/python/gem5/components/processors/linear_generator_core.py

@@ -24,16 +24,22 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.ticks import fromSeconds
-from m5.util.convert import toLatency, toMemoryBandwidth
-from m5.objects import PyTrafficGen, Port, BaseTrafficGen
+from typing import Iterator
 
-from .abstract_core import AbstractCore
-from .abstract_generator_core import AbstractGeneratorCore
+from m5.objects import (
+    BaseTrafficGen,
+    Port,
+    PyTrafficGen,
+)
+from m5.ticks import fromSeconds
+from m5.util.convert import (
+    toLatency,
+    toMemoryBandwidth,
+)
 
 from ...utils.override import overrides
-
-from typing import Iterator
+from .abstract_core import AbstractCore
+from .abstract_generator_core import AbstractGeneratorCore
 
 
 class LinearGeneratorCore(AbstractGeneratorCore):

src/python/gem5/components/processors/random_generator.py

@@ -24,15 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ...utils.override import overrides
-from ..boards.mem_mode import MemMode
-from .random_generator_core import RandomGeneratorCore
-
-from .abstract_generator import AbstractGenerator
-from ..boards.abstract_board import AbstractBoard
-
 from typing import List
 
+from ...utils.override import overrides
+from ..boards.abstract_board import AbstractBoard
+from ..boards.mem_mode import MemMode
+from .abstract_generator import AbstractGenerator
+from .random_generator_core import RandomGeneratorCore
+
 
 class RandomGenerator(AbstractGenerator):
     def __init__(

src/python/gem5/components/processors/random_generator_core.py

@@ -24,16 +24,22 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.ticks import fromSeconds
-from m5.util.convert import toLatency, toMemoryBandwidth
-from m5.objects import PyTrafficGen, Port, BaseTrafficGen
+from typing import Iterator
 
-from .abstract_core import AbstractCore
-from .abstract_generator_core import AbstractGeneratorCore
+from m5.objects import (
+    BaseTrafficGen,
+    Port,
+    PyTrafficGen,
+)
+from m5.ticks import fromSeconds
+from m5.util.convert import (
+    toLatency,
+    toMemoryBandwidth,
+)
 
 from ...utils.override import overrides
-
-from typing import Iterator
+from .abstract_core import AbstractCore
+from .abstract_generator_core import AbstractGeneratorCore
 
 
 class RandomGeneratorCore(AbstractGeneratorCore):

src/python/gem5/components/processors/simple_core.py

@@ -24,15 +24,15 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import importlib
+import platform
 from typing import Optional
+
+from ...isas import ISA
+from ...runtime import get_runtime_isa
 from ...utils.requires import requires
 from .base_cpu_core import BaseCPUCore
 from .cpu_types import CPUTypes
-from ...isas import ISA
-from ...utils.requires import requires
-from ...runtime import get_runtime_isa
-import importlib
-import platform
 
 
 class SimpleCore(BaseCPUCore):

src/python/gem5/components/processors/simple_processor.py

@@ -25,15 +25,15 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from m5.util import warn
-from .base_cpu_processor import BaseCPUProcessor
-from ..processors.simple_core import SimpleCore
-
-from .cpu_types import CPUTypes
-from ...isas import ISA
-
 from typing import Optional
 
+from m5.util import warn
+
+from ...isas import ISA
+from ..processors.simple_core import SimpleCore
+from .base_cpu_processor import BaseCPUProcessor
+from .cpu_types import CPUTypes
+
 
 class SimpleProcessor(BaseCPUProcessor):
     """

src/python/gem5/components/processors/simple_switchable_processor.py

@@ -24,17 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ..boards.mem_mode import MemMode
-from ..boards.abstract_board import AbstractBoard
-from ..processors.simple_core import SimpleCore
-from ..processors.cpu_types import CPUTypes, get_mem_mode
-from .switchable_processor import SwitchableProcessor
-from ...isas import ISA
+from typing import Optional
+
 from m5.util import warn
 
+from ...isas import ISA
 from ...utils.override import *
-
-from typing import Optional
+from ..boards.abstract_board import AbstractBoard
+from ..boards.mem_mode import MemMode
+from ..processors.cpu_types import (
+    CPUTypes,
+    get_mem_mode,
+)
+from ..processors.simple_core import SimpleCore
+from .switchable_processor import SwitchableProcessor
 
 
 class SimpleSwitchableProcessor(SwitchableProcessor):

src/python/gem5/components/processors/switchable_processor.py

@@ -25,17 +25,19 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from .simple_core import SimpleCore
-from .abstract_core import AbstractCore
-from .cpu_types import CPUTypes
+from typing import (
+    Dict,
+    List,
+)
 
 import m5
 
-from typing import Dict, List
-
-from .abstract_processor import AbstractProcessor
-from ..boards.abstract_board import AbstractBoard
 from ...utils.override import *
+from ..boards.abstract_board import AbstractBoard
+from .abstract_core import AbstractCore
+from .abstract_processor import AbstractProcessor
+from .cpu_types import CPUTypes
+from .simple_core import SimpleCore
 
 
 class SwitchableProcessor(AbstractProcessor):

src/python/gem5/components/processors/traffic_generator.py

@@ -24,13 +24,12 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from ...utils.override import overrides
-from .traffic_generator_core import TrafficGeneratorCore
-
-from .abstract_generator import AbstractGenerator
-
 from typing import List
 
+from ...utils.override import overrides
+from .abstract_generator import AbstractGenerator
+from .traffic_generator_core import TrafficGeneratorCore
+
 
 class TrafficGenerator(AbstractGenerator):
     def __init__(

src/python/gem5/components/processors/traffic_generator_core.py

@@ -25,11 +25,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 
-from m5.objects import Port, TrafficGen
+from m5.objects import (
+    Port,
+    TrafficGen,
+)
 
+from ...utils.override import overrides
 from .abstract_core import AbstractCore
 from .abstract_generator_core import AbstractGeneratorCore
-from ...utils.override import overrides
 
 
 class TrafficGeneratorCore(AbstractGeneratorCore):

src/python/gem5/prebuilt/demo/x86_demo_board.py

@@ -26,14 +26,14 @@
 
 from m5.util import warn
 
-from ...components.processors.cpu_types import CPUTypes
+from ...coherence_protocol import CoherenceProtocol
 from ...components.boards.x86_board import X86Board
-from ...components.memory.single_channel import SingleChannelDDR3_1600
-from ...components.processors.simple_processor import SimpleProcessor
 from ...components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy import (
     MESITwoLevelCacheHierarchy,
 )
-from ...coherence_protocol import CoherenceProtocol
+from ...components.memory.single_channel import SingleChannelDDR3_1600
+from ...components.processors.cpu_types import CPUTypes
+from ...components.processors.simple_processor import SimpleProcessor
 from ...isas import ISA
 from ...utils.requires import requires
 

src/python/gem5/prebuilt/riscvmatched/riscvmatched_board.py

@@ -27,42 +27,30 @@
 
 import os
 import re
-
-from typing import List, Optional
-
-from gem5.utils.override import overrides
-from gem5.components.boards.abstract_system_board import AbstractSystemBoard
-from gem5.components.boards.kernel_disk_workload import KernelDiskWorkload
-from gem5.components.boards.se_binary_workload import SEBinaryWorkload
-from gem5.resources.resource import AbstractResource
-from gem5.components.memory import SingleChannelDDR4_2400
-from gem5.utils.requires import requires
-from gem5.isas import ISA
-from .riscvmatched_cache import RISCVMatchedCacheHierarchy
-from .riscvmatched_processor import U74Processor
-from gem5.isas import ISA
-
-import m5
-
-from m5.objects import (
-    BadAddr,
-    Bridge,
-    PMAChecker,
-    RiscvLinux,
-    AddrRange,
-    IOXBar,
-    RiscvRTC,
-    HiFive,
-    IGbE_e1000,
-    CowDiskImage,
-    RawDiskImage,
-    RiscvMmioVirtIO,
-    VirtIOBlock,
-    VirtIORng,
-    Frequency,
-    Port,
+from typing import (
+    List,
+    Optional,
 )
 
+import m5
+from m5.objects import (
+    AddrRange,
+    BadAddr,
+    Bridge,
+    CowDiskImage,
+    Frequency,
+    HiFive,
+    IGbE_e1000,
+    IOXBar,
+    PMAChecker,
+    Port,
+    RawDiskImage,
+    RiscvLinux,
+    RiscvMmioVirtIO,
+    RiscvRTC,
+    VirtIOBlock,
+    VirtIORng,
+)
 from m5.util.fdthelper import (
     Fdt,
     FdtNode,
@@ -72,6 +60,18 @@ from m5.util.fdthelper import (
     FdtState,
 )
 
+from gem5.components.boards.abstract_system_board import AbstractSystemBoard
+from gem5.components.boards.kernel_disk_workload import KernelDiskWorkload
+from gem5.components.boards.se_binary_workload import SEBinaryWorkload
+from gem5.components.memory import SingleChannelDDR4_2400
+from gem5.isas import ISA
+from gem5.resources.resource import AbstractResource
+from gem5.utils.override import overrides
+from gem5.utils.requires import requires
+
+from .riscvmatched_cache import RISCVMatchedCacheHierarchy
+from .riscvmatched_processor import U74Processor
+
 
 def U74Memory():
     """

src/python/gem5/prebuilt/riscvmatched/riscvmatched_cache.py

@@ -24,25 +24,33 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from typing import Type
+
+from m5.objects import (
+    BadAddr,
+    BaseXBar,
+    Cache,
+    L2XBar,
+    Port,
+    SystemXBar,
+)
+
+from gem5.components.boards.abstract_board import AbstractBoard
 from gem5.components.cachehierarchies.abstract_cache_hierarchy import (
     AbstractCacheHierarchy,
 )
-from gem5.components.cachehierarchies.classic.abstract_classic_cache_hierarchy import (
-    AbstractClassicCacheHierarchy,
-)
 from gem5.components.cachehierarchies.abstract_two_level_cache_hierarchy import (
     AbstractTwoLevelCacheHierarchy,
 )
+from gem5.components.cachehierarchies.classic.abstract_classic_cache_hierarchy import (
+    AbstractClassicCacheHierarchy,
+)
 from gem5.components.cachehierarchies.classic.caches.l1dcache import L1DCache
 from gem5.components.cachehierarchies.classic.caches.l1icache import L1ICache
 from gem5.components.cachehierarchies.classic.caches.l2cache import L2Cache
 from gem5.components.cachehierarchies.classic.caches.mmu_cache import MMUCache
-from gem5.components.boards.abstract_board import AbstractBoard
 from gem5.isas import ISA
-from m5.objects import Cache, L2XBar, BaseXBar, SystemXBar, BadAddr, Port
-
 from gem5.utils.override import *
-from typing import Type
 
 
 class RISCVMatchedCacheHierarchy(

src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

@@ -25,20 +25,21 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from typing import Optional
-from gem5.utils.requires import requires
+
+from m5.objects import (
+    BaseCPU,
+    BaseMMU,
+    Port,
+    Process,
+)
+from m5.objects.BaseMinorCPU import *
+from m5.objects.RiscvCPU import RiscvMinorCPU
+
 from gem5.components.processors.base_cpu_core import BaseCPUCore
 from gem5.components.processors.cpu_types import CPUTypes
 from gem5.isas import ISA
 from gem5.utils.override import overrides
-from m5.objects.RiscvCPU import RiscvMinorCPU
-from m5.objects import (
-    BaseMMU,
-    Port,
-    BaseCPU,
-    Process,
-)
-from m5.objects.BaseMinorCPU import *
-from gem5.isas import ISA
+from gem5.utils.requires import requires
 
 
 class U74IntFU(MinorDefaultIntFU):

src/python/gem5/prebuilt/riscvmatched/riscvmatched_processor.py

@@ -24,14 +24,14 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from gem5.utils.override import overrides
-from gem5.components.boards.mem_mode import MemMode
-
 from m5.util import warn
 
+from gem5.components.boards.abstract_board import AbstractBoard
+from gem5.components.boards.mem_mode import MemMode
 from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
 from gem5.components.processors.cpu_types import CPUTypes
-from gem5.components.boards.abstract_board import AbstractBoard
+from gem5.utils.override import overrides
+
 from .riscvmatched_core import U74Core
 
 

src/python/gem5/resources/client.py

@@ -25,14 +25,25 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 import json
-from pathlib import Path
 import os
-from typing import Optional, Dict, List
-from .client_api.client_wrapper import ClientWrapper
-from gem5.gem5_default_config import config
-from m5.util import inform, warn
+from pathlib import Path
+from typing import (
+    Dict,
+    List,
+    Optional,
+)
+
+from m5.util import (
+    inform,
+    warn,
+)
+
 from _m5 import core
 
+from gem5.gem5_default_config import config
+
+from .client_api.client_wrapper import ClientWrapper
+
 
 def getFileContent(file_path: Path) -> Dict:
     """

src/python/gem5/resources/client_api/abstract_client.py

@@ -24,9 +24,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABC, abstractmethod
-from typing import Any, Dict, List, Optional
 import urllib.parse
+from abc import (
+    ABC,
+    abstractmethod,
+)
+from typing import (
+    Any,
+    Dict,
+    List,
+    Optional,
+)
 
 
 class AbstractClient(ABC):

src/python/gem5/resources/client_api/atlasclient.py

@@ -24,14 +24,27 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from urllib import request, parse
-from typing import Optional, Dict, Union, Type, Tuple, List, Any
+import itertools
 import json
 import time
-import itertools
-from .abstract_client import AbstractClient
+from typing import (
+    Any,
+    Dict,
+    List,
+    Optional,
+    Tuple,
+    Type,
+    Union,
+)
+from urllib import (
+    parse,
+    request,
+)
+
 from m5.util import warn
 
+from .abstract_client import AbstractClient
+
 
 class AtlasClientHttpJsonRequestError(Exception):
     def __init__(

src/python/gem5/resources/client_api/client_wrapper.py

@@ -24,13 +24,21 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .jsonclient import JSONClient
-from .atlasclient import AtlasClient
-from _m5 import core
-from typing import Optional, Dict, List, Tuple
 import itertools
-from m5.util import warn
 import sys
+from typing import (
+    Dict,
+    List,
+    Optional,
+    Tuple,
+)
+
+from m5.util import warn
+
+from _m5 import core
+
+from .atlasclient import AtlasClient
+from .jsonclient import JSONClient
 
 
 class ClientWrapper:

src/python/gem5/resources/client_api/jsonclient.py

@@ -26,12 +26,22 @@
 
 import json
 from pathlib import Path
+from typing import (
+    Any,
+    Dict,
+    List,
+    Optional,
+    Tuple,
+    Type,
+    Union,
+)
 from urllib import request
-from typing import Optional, Dict, Union, Type, Tuple, List, Any
-from .abstract_client import AbstractClient
 from urllib.error import URLError
+
 from m5.util import warn
 
+from .abstract_client import AbstractClient
+
 
 class JSONClient(AbstractClient):
     def __init__(self, path: str):

src/python/gem5/resources/downloader.py

@@ -24,29 +24,36 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import urllib.request
-import urllib.parse
-import os
-import shutil
 import gzip
-import time
+import os
 import random
-from pathlib import Path
+import shutil
 import tarfile
+import time
+import urllib.parse
+import urllib.request
+from pathlib import Path
+from typing import (
+    Dict,
+    List,
+    Optional,
+)
 from urllib.error import HTTPError
 from urllib.parse import urlparse
-from typing import List, Optional, Dict
 
 from _m5 import core
 
-from .client import (
-    get_resource_json_obj,
-    list_resources as client_list_resources,
-)
-from .md5_utils import md5_file, md5_dir
-from ..utils.progress_bar import tqdm, progress_hook
-
 from ..utils.filelock import FileLock
+from ..utils.progress_bar import (
+    progress_hook,
+    tqdm,
+)
+from .client import get_resource_json_obj
+from .client import list_resources as client_list_resources
+from .md5_utils import (
+    md5_dir,
+    md5_file,
+)
 
 """
 This Python module contains functions used to download, list, and obtain
@@ -86,10 +93,11 @@ def _download(url: str, download_to: str, max_attempts: int = 6) -> None:
                 # If the "use_proxy" variable is specified we setup a socks5
                 # connection.
 
-                import socks
                 import socket
                 import ssl
 
+                import socks
+
                 IP_ADDR, host_port = use_proxy.split(":")
                 PORT = int(host_port)
                 socks.set_default_proxy(socks.SOCKS5, IP_ADDR, PORT)

src/python/gem5/resources/elfie.py

@@ -24,11 +24,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import PcCountPair
-from m5.objects import PcCountTrackerManager
-
 from typing import List
 
+from m5.objects import PcCountTrackerManager
+from m5.params import PcCountPair
+
 
 class ELFieInfo:
     """Stores information to load/run ELFies

src/python/gem5/resources/looppoint.py

@@ -24,15 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import PcCountPair
-from m5.objects import PcCountTrackerManager
-import m5
-
-import os
 import csv
 import json
+import os
 from pathlib import Path
-from typing import List, Optional, Dict, Union
+from typing import (
+    Dict,
+    List,
+    Optional,
+    Union,
+)
+
+import m5
+from m5.objects import PcCountTrackerManager
+from m5.params import PcCountPair
 
 
 class LooppointRegionPC:

src/python/gem5/resources/md5_utils.py

@@ -25,9 +25,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import hashlib
 from pathlib import Path
 from typing import Type
-import hashlib
 
 
 def _md5_update_from_file(

src/python/gem5/resources/resource.py

@@ -24,31 +24,39 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from abc import ABCMeta
 import json
 import os
+from abc import ABCMeta
 from pathlib import Path
-from m5.util import warn, fatal
-from _m5 import core
-
-from .downloader import get_resource
-
-from .looppoint import LooppointCsvLoader, LooppointJsonLoader
-from ..isas import ISA, get_isa_from_str
-
 from typing import (
-    Optional,
-    Dict,
-    Union,
-    Type,
-    Tuple,
-    List,
     Any,
-    Set,
+    Dict,
     Generator,
+    List,
+    Optional,
+    Set,
+    Tuple,
+    Type,
+    Union,
 )
 
+from m5.util import (
+    fatal,
+    warn,
+)
+
+from _m5 import core
+
+from ..isas import (
+    ISA,
+    get_isa_from_str,
+)
 from .client import get_resource_json_obj
+from .downloader import get_resource
+from .looppoint import (
+    LooppointCsvLoader,
+    LooppointJsonLoader,
+)
 
 """
 Resources are items needed to run a simulation, such as a disk image, kernel,

src/python/gem5/resources/workload.py

@@ -24,13 +24,22 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .resource import obtain_resource, WorkloadResource
-from .client import get_resource_json_obj
+from typing import (
+    Any,
+    Dict,
+    List,
+    Optional,
+)
 
-from _m5 import core
 from m5.util import warn
 
-from typing import Dict, Any, List, Optional
+from _m5 import core
+
+from .client import get_resource_json_obj
+from .resource import (
+    WorkloadResource,
+    obtain_resource,
+)
 
 
 def CustomWorkload(function: str, parameters: Dict[str, Any]):

src/python/gem5/runtime.py

@@ -28,12 +28,17 @@
 This file contains functions to extract gem5 runtime information.
 """
 
+from typing import Set
+
 from m5.defines import buildEnv
 from m5.util import warn
 
-from .isas import ISA, get_isa_from_str, get_isas_str_set
 from .coherence_protocol import CoherenceProtocol
-from typing import Set
+from .isas import (
+    ISA,
+    get_isa_from_str,
+    get_isas_str_set,
+)
 
 
 def get_supported_isas() -> Set[ISA]:

src/python/gem5/simulate/exit_event_generators.py

@@ -24,14 +24,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Generator, Optional
+from pathlib import Path
+from typing import (
+    Generator,
+    Optional,
+)
+
 import m5.stats
+from m5.util import warn
+
+from gem5.resources.looppoint import Looppoint
+
 from ..components.processors.abstract_processor import AbstractProcessor
 from ..components.processors.switchable_processor import SwitchableProcessor
 from ..resources.resource import SimpointResource
-from gem5.resources.looppoint import Looppoint
-from m5.util import warn
-from pathlib import Path
 
 """
 In this package we store generators for simulation exit events.

src/python/gem5/simulate/simulator.py

@@ -24,29 +24,37 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-import m5
-import m5.ticks
-from m5.stats import addStatVisitor
-from m5.ext.pystats.simstat import SimStat
-from m5.objects import Root
-from m5.util import warn
-
 import os
 import sys
 from pathlib import Path
-from typing import Optional, List, Tuple, Dict, Generator, Union, Callable
-
-from .exit_event_generators import (
-    warn_default_decorator,
-    exit_generator,
-    switch_generator,
-    save_checkpoint_generator,
-    reset_stats_generator,
-    dump_stats_generator,
+from typing import (
+    Callable,
+    Dict,
+    Generator,
+    List,
+    Optional,
+    Tuple,
+    Union,
 )
-from .exit_event import ExitEvent
+
+import m5
+import m5.ticks
+from m5.ext.pystats.simstat import SimStat
+from m5.objects import Root
+from m5.stats import addStatVisitor
+from m5.util import warn
+
 from ..components.boards.abstract_board import AbstractBoard
 from ..components.processors.switchable_processor import SwitchableProcessor
+from .exit_event import ExitEvent
+from .exit_event_generators import (
+    dump_stats_generator,
+    exit_generator,
+    reset_stats_generator,
+    save_checkpoint_generator,
+    switch_generator,
+    warn_default_decorator,
+)
 
 
 class Simulator:

src/python/gem5/utils/filelock.py

@@ -23,9 +23,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+import errno
 import os
 import time
-import errno
 
 
 class FileLockException(Exception):

src/python/gem5/utils/multiprocessing/__init__.py

@@ -24,9 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from .context import Process
-
-from .context import gem5Context
+from .context import (
+    Process,
+    gem5Context,
+)
 
 Pool = gem5Context().Pool
 

src/python/gem5/utils/multiprocessing/_command_line.py

@@ -32,7 +32,10 @@ multiprocessing module (i.e., cpython/Lib/multiprocessing/).
 """
 
 import sys
-from multiprocessing import spawn, util
+from multiprocessing import (
+    spawn,
+    util,
+)
 
 
 def _gem5_args_for_multiprocessing(name):