d11c40dcac
This ensures `isort` is applied to all files in the repo. Change-Id: Ib7ced1c924ef1639542bf0d1a01c5737f6ba43e9
111 lines
3.5 KiB
Python
111 lines
3.5 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from typing import Optional
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from .abstract_memory_system import AbstractMemorySystem
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from .dram_interfaces.ddr3 import (
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DDR3_1600_8x8,
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DDR3_2133_8x8,
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)
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from .dram_interfaces.ddr4 import DDR4_2400_8x8
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from .dram_interfaces.ddr5 import (
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DDR5_4400_4x8,
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DDR5_6400_4x8,
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DDR5_8400_4x8,
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)
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from .dram_interfaces.hbm import HBM_1000_4H_1x128
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from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
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from .memory import ChanneledMemory
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def SingleChannelDDR3_1600(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single channel memory system using DDR3_1600_8x8 based DIMM
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"""
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return ChanneledMemory(DDR3_1600_8x8, 1, 64, size=size)
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def SingleChannelDDR3_2133(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single channel memory system using DDR3_2133_8x8 based DIMM
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"""
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return ChanneledMemory(DDR3_2133_8x8, 1, 64, size=size)
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def SingleChannelDDR4_2400(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single channel memory system using DDR4_2400_8x8 based DIMM
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"""
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return ChanneledMemory(DDR4_2400_8x8, 1, 64, size=size)
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def SingleChannelLPDDR3_1600(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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return ChanneledMemory(LPDDR3_1600_1x32, 1, 64, size=size)
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def SingleChannelHBM(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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if not size:
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size = "256MiB"
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return ChanneledMemory(HBM_1000_4H_1x128, 1, 64, size=size)
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def DIMM_DDR5_4400(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single DIMM of DDR5 has two channels
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"""
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return ChanneledMemory(DDR5_4400_4x8, 2, 64, size=size)
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def DIMM_DDR5_6400(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single DIMM of DDR5 has two channels
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"""
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return ChanneledMemory(DDR5_6400_4x8, 2, 64, size=size)
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def DIMM_DDR5_8400(
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size: Optional[str] = None,
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) -> AbstractMemorySystem:
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"""
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A single DIMM of DDR5 has two channels
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"""
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return ChanneledMemory(DDR5_8400_4x8, 2, 64, size=size)
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