misc,python: Add isort hook to pre-commit (#431)

src/cpu/BaseCPU.py

@@ -40,20 +40,19 @@
 
 import sys
 
-from m5.SimObject import *
 from m5.defines import buildEnv
-from m5.params import *
-from m5.proxy import *
-from m5.util.fdthelper import *
-
-from m5.objects.ClockedObject import ClockedObject
-from m5.objects.XBar import L2XBar
-from m5.objects.InstTracer import InstTracer
-from m5.objects.CPUTracers import ExeTracer
-from m5.objects.SubSystem import SubSystem
 from m5.objects.ClockDomain import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.InstTracer import InstTracer
 from m5.objects.Platform import Platform
 from m5.objects.ResetPort import ResetResponsePort
+from m5.objects.SubSystem import SubSystem
+from m5.objects.XBar import L2XBar
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import *
+from m5.util.fdthelper import *
 
 default_tracer = ExeTracer()
 

src/cpu/CPUTracers.py

@@ -24,9 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.InstTracer import InstTracer
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class ExeTracer(InstTracer):

src/cpu/Capstone.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.InstTracer import InstDisassembler
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class CapstoneDisassembler(InstDisassembler):

src/cpu/CheckerCPU.py

@@ -24,9 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.BaseCPU import BaseCPU
+from m5.params import *
 from m5.SimObject import SimObject
 
 

src/cpu/CpuCluster.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.SubSystem import SubSystem
+from m5.params import *
 
 
 class CpuCluster(SubSystem):

src/cpu/DummyChecker.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.CheckerCPU import CheckerCPU
+from m5.params import *
 
 
 class DummyChecker(CheckerCPU):

src/cpu/FuncUnit.py

@@ -36,8 +36,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.params import *
+from m5.SimObject import SimObject
 
 
 class OpClass(Enum):

src/cpu/InstPBTrace.py

@@ -24,10 +24,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
-
 from m5.objects.InstTracer import InstTracer
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class InstPBTrace(InstTracer):

src/cpu/kvm/BaseKvmCPU.py

@@ -33,12 +33,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import *
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseCPU import BaseCPU
 from m5.objects.KvmVM import KvmVM
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import *
 
 
 class BaseKvmCPU(BaseCPU):

src/cpu/kvm/KvmVM.py

@@ -35,7 +35,6 @@
 
 from m5.params import *
 from m5.proxy import *
-
 from m5.SimObject import SimObject
 
 

src/cpu/minor/BaseMinorCPU.py

@@ -37,15 +37,14 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.BranchPredictor import *
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.FuncUnit import OpClass
+from m5.objects.TimingExpr import TimingExpr
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from m5.objects.BaseCPU import BaseCPU
-from m5.objects.DummyChecker import DummyChecker
-from m5.objects.BranchPredictor import *
-from m5.objects.TimingExpr import TimingExpr
-
-from m5.objects.FuncUnit import OpClass
 
 
 class MinorOpClass(SimObject):

src/cpu/o3/BaseO3CPU.py

@@ -37,14 +37,13 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.params import *
-from m5.proxy import *
-
 from m5.objects.BaseCPU import BaseCPU
-from m5.objects.FUPool import *
 
 # from m5.objects.O3Checker import O3Checker
 from m5.objects.BranchPredictor import *
+from m5.objects.FUPool import *
+from m5.params import *
+from m5.proxy import *
 
 
 class SMTFetchPolicy(ScopedEnum):

src/cpu/o3/BaseO3Checker.py

@@ -24,8 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.CheckerCPU import CheckerCPU
+from m5.params import *
 
 
 class BaseO3Checker(CheckerCPU):

src/cpu/o3/FUPool.py

@@ -36,10 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
-from m5.params import *
 from m5.objects.FuncUnit import *
 from m5.objects.FuncUnitConfig import *
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class FUPool(SimObject):

src/cpu/o3/FuncUnitConfig.py

@@ -36,11 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
 from m5.defines import buildEnv
-from m5.params import *
-
 from m5.objects.FuncUnit import *
+from m5.params import *
+from m5.SimObject import SimObject
 
 
 class IntALU(FUDesc):

src/cpu/pred/BranchPredictor.py

@@ -37,11 +37,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import *
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import *
 
 
 class BranchType(Enum):

src/cpu/probes/PcCountTracker.py

@@ -24,10 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects import SimObject
+from m5.objects.Probe import ProbeListenerObject
 from m5.params import *
 from m5.util.pybind import *
-from m5.objects.Probe import ProbeListenerObject
-from m5.objects import SimObject
 
 
 class PcCountTrackerManager(SimObject):

src/cpu/simple/BaseAtomicSimpleCPU.py

@@ -36,9 +36,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseSimpleCPU import BaseSimpleCPU
 from m5.objects.SimPoint import SimPoint
+from m5.params import *
 
 
 class BaseAtomicSimpleCPU(BaseSimpleCPU):

src/cpu/simple/BaseNonCachingSimpleCPU.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
+from m5.params import *
 
 
 class BaseNonCachingSimpleCPU(BaseAtomicSimpleCPU):

src/cpu/simple/BaseSimpleCPU.py

@@ -25,11 +25,10 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.params import *
-
 from m5.objects.BaseCPU import BaseCPU
-from m5.objects.DummyChecker import DummyChecker
 from m5.objects.BranchPredictor import *
+from m5.objects.DummyChecker import DummyChecker
+from m5.params import *
 
 
 class BaseSimpleCPU(BaseCPU):

src/cpu/simple/BaseTimingSimpleCPU.py

@@ -24,9 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
-
 from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.params import *
 
 
 class BaseTimingSimpleCPU(BaseSimpleCPU):

src/cpu/simple/probes/SimPoint.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.Probe import ProbeListenerObject
+from m5.params import *
 
 
 class SimPoint(ProbeListenerObject):

src/cpu/testers/directedtest/RubyDirectedTester.py

@@ -24,11 +24,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.SimObject import SimObject
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-
-from m5.objects.ClockedObject import ClockedObject
+from m5.SimObject import SimObject
 
 
 class DirectedGenerator(SimObject):

src/cpu/testers/gpu_ruby_test/CpuThread.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class CpuThread(TesterThread):
     type = "CpuThread"

src/cpu/testers/gpu_ruby_test/DmaThread.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class DmaThread(TesterThread):
     type = "DmaThread"

src/cpu/testers/gpu_ruby_test/GpuWavefront.py

@@ -27,11 +27,10 @@
 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 # POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.TesterThread import TesterThread
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.TesterThread import TesterThread
-
 
 class GpuWavefront(TesterThread):
     type = "GpuWavefront"

src/cpu/testers/memtest/MemTest.py

@@ -36,11 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.ClockedObject import ClockedObject
-
 
 class MemTest(ClockedObject):
     type = "MemTest"

src/cpu/testers/rubytest/RubyTester.py

@@ -25,11 +25,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
 
-from m5.objects.ClockedObject import ClockedObject
-
 
 class RubyTester(ClockedObject):
     type = "RubyTester"

src/cpu/testers/traffic_gen/BaseTrafficGen.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 # Types of Stream Generators.

src/cpu/testers/traffic_gen/GUPSGen.py

@@ -25,9 +25,9 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 class GUPSGen(ClockedObject):

src/cpu/testers/traffic_gen/PyTrafficGen.py

@@ -34,9 +34,8 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 from m5.defines import buildEnv
-from m5.SimObject import *
-
 from m5.objects.BaseTrafficGen import *
+from m5.SimObject import *
 
 
 class PyTrafficGen(BaseTrafficGen):

src/cpu/testers/traffic_gen/TrafficGen.py

@@ -33,8 +33,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from m5.params import *
 from m5.objects.BaseTrafficGen import *
+from m5.params import *
 
 
 # The behaviour of this traffic generator is specified in a

src/cpu/trace/TraceCPU.py

@@ -33,9 +33,9 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+from m5.objects.ClockedObject import ClockedObject
 from m5.params import *
 from m5.proxy import *
-from m5.objects.ClockedObject import ClockedObject
 
 
 class TraceCPU(ClockedObject):