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arch-arm: ISV bit in DataAbort should check for translation stage

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According to the ESR spec, the ISV bit is set to 1 only for stage 2
aborts.

Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2019-09-06 14:44:47 +01:00
parent 0e4c3437fd
commit dc70987e47
1 changed files with 1 additions and 1 deletions
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2
src/arch/arm/faults.cc
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@@ -1371,7 +1371,7 @@ DataAbort::iss() const
val = AbortFault<DataAbort>::iss();
// ISS is valid if not caused by a stage 1 page table walk, and when taken
// to AArch64 only when directed to EL2
if (!s1ptw && (!to64 || toEL == EL2)) {
if (!s1ptw && stage2 && (!to64 || toEL == EL2)) {
val |= isv << 24;
if (isv) {
val |= sas << 22;