cpu,arch-arm,arch-riscv: adding new instruction types to RISC-V (#589)

This commit adds more detailed instruction types for RISC-V Vector.
Concretely, it substitutes VectorIntegerArith, VectorFloatArith,
VectorIntegerReduce and VectorFloatReduce with more specific types
related to the operation that each instruction (e.g., VectorIntegerAdd
or VectorIntegerMult).

Additionaly, fixes two RISC-V instruction types (VectorXXX) that were
used in ARM SVE, placing the proper SimdXXX ones.

Change-Id: I31774fa6a7cd249abfffec68d11d3d77f08ad70b

CC @adriaarmejach

src/python/gem5/prebuilt/riscvmatched/riscvmatched_core.py

@@ -76,10 +76,6 @@ class U74MiscFU(MinorDefaultMiscFU):
     pass
 
 
-class U74VecFU(MinorDefaultVecFU):
-    pass
-
-
 class U74FUPool(MinorFUPool):
     funcUnits = [
         U74IntFU(),
@@ -91,7 +87,6 @@ class U74FUPool(MinorFUPool):
         U74MemReadFU(),
         U74MemWriteFU(),
         U74MiscFU(),
-        U74VecFU(),
     ]