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Make the register indices use the appropriate "fold" bit.

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--HG--
extra : convert_revision : 89e15e2ef1f709f2c09238b78f94505ce8ef146d
This commit is contained in:
Gabe Black
2007-07-30 13:25:00 -07:00
parent d8beeff324
commit da84aa95a9
2 changed files with 14 additions and 9 deletions
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14
src/arch/x86/isa/operands.isa
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@@ -96,13 +96,13 @@ def operand_types {{
}};
def operands {{
'DestReg': ('IntReg', 'uqw', 'dest', 'IsInteger', 1),
'SrcReg1': ('IntReg', 'uqw', 'src1', 'IsInteger', 2),
'SrcReg2': ('IntReg', 'uqw', 'src2', 'IsInteger', 3),
'Base': ('IntReg', 'uqw', 'base', 'IsInteger', 4),
'Index': ('IntReg', 'uqw', 'index', 'IsInteger', 5),
'Data': ('IntReg', 'uqw', 'data', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', 'INTREG_RAX', 'IsInteger', 7),
'SrcReg1': ('IntReg', 'uqw', '(((src1 & 0xC) == 4 ? foldOBit : 0) | src1)', 'IsInteger', 1),
'SrcReg2': ('IntReg', 'uqw', '(((src2 & 0xC) == 4 ? foldOBit : 0) | src2)', 'IsInteger', 2),
'Base': ('IntReg', 'uqw', '(((base & 0xC) == 4 ? foldABit : 0) | base)', 'IsInteger', 3),
'Index': ('IntReg', 'uqw', '(((index & 0xC) == 4 ? foldABit : 0) | index)', 'IsInteger', 4),
'DestReg': ('IntReg', 'uqw', '(((dest & 0xC) == 4 ? foldOBit : 0) | dest)', 'IsInteger', 5),
'Data': ('IntReg', 'uqw', '(((data & 0xC) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
'rax': ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
'RIP': ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
'ccFlagBits': ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
'Mem': ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)

9
src/arch/x86/regfile.cc
View File

@@ -86,6 +86,7 @@
*/
#include "arch/x86/regfile.hh"
#include "base/trace.hh"
#include "sim/serialize.hh"
#include "cpu/thread_context.hh"
@@ -209,8 +210,12 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
{
//For right now, don't do any flattening
return reg;
//If we need to fold over the index to match byte semantics, do that.
//Otherwise, just strip off any extra bits and pass it through.
if (reg & (1 << 6))
return (reg & ~(1 << 6) - 0x4);
else
return (reg & ~(1 << 6));
}
void RegFile::serialize(std::ostream &os)