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alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.

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It's no longer used.

Change-Id: I4a71bcb214f1bb186b92ef50841eca635e6701c5
Reviewed-on: https://gem5-review.googlesource.com/6826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2017-12-20 00:06:07 -08:00
parent 87eb9a3a64
commit da79d6c6cd
7 changed files with 0 additions and 35 deletions
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4
src/arch/alpha/isa_traits.hh
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@@ -111,10 +111,6 @@ enum mode_type
const int MachineBytes = 8;
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
const ExtMachInst NoopMachInst = 0x2ffe0000;
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;

3
src/arch/arm/isa_traits.hh
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@@ -96,9 +96,6 @@ namespace ArmISA
// Max. physical address range in bits supported by the architecture
const unsigned MaxPhysAddrRange = 48;
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x01E320F000ULL;
const int MachineBytes = 4;
const uint32_t HighVecs = 0xFFFF0000;

3
src/arch/mips/isa_traits.hh
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@@ -142,9 +142,6 @@ enum mode_type
mode_number // number of modes
};
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;

3
src/arch/power/isa_traits.hh
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@@ -63,9 +63,6 @@ const Addr PteMask = NPtePage - 1;
const int MachineBytes = 4;
// This is ori 0, 0, 0
const ExtMachInst NoopMachInst = 0x60000000;
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;

2
src/arch/riscv/isa_traits.hh
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@@ -63,8 +63,6 @@ using namespace LittleEndianGuest;
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const ExtMachInst NoopMachInst = 0x00000013;
// Memory accesses can be unaligned (at least for double-word memory accesses)
const bool HasUnalignedMemAcc = true;

3
src/arch/sparc/isa_traits.hh
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@@ -47,9 +47,6 @@ using namespace BigEndianGuest;
// SPARC has a delay slot
#define ISA_HAS_DELAY_SLOT 1
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);

17
src/arch/x86/isa_traits.hh
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@@ -56,10 +56,6 @@ namespace X86ISA
// X86 does not have a delay slot
#define ISA_HAS_DELAY_SLOT 0
// X86 NOP (XCHG rAX, rAX)
//XXX This needs to be set to an intermediate instruction struct
//which encodes this instruction
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
@@ -68,19 +64,6 @@ namespace X86ISA
const bool CurThreadInfoImplemented = false;
const int CurThreadInfoReg = -1;
const ExtMachInst NoopMachInst M5_VAR_USED = {
0x0, // No legacy prefixes.
0x0, // No rex prefix.
0x0, // No two / three byte escape sequence
{ OneByteOpcode, 0x90 }, // One opcode byte, 0x90.
0x0, 0x0, // No modrm or sib.
0, 0, // No immediate or displacement.
8, 8, 8, // All sizes are 8.
0, // Displacement size is 0.
SixtyFourBitMode // Behave as if we're in 64 bit
// mode (this doesn't actually matter).
};
}
#endif // __ARCH_X86_ISATRAITS_HH__