X86: Make conditional moves zero extend their 32 bit destinations always.

2009-08-05 03:07:55 -07:00
parent b64d0bdeda
commit da2df2fc25
1 changed files with 1 additions and 1 deletions
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -639,7 +639,7 @@ let {{

    class Mov(CondRegOp):
        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
-        else_code = 'DestReg=DestReg;'
+        else_code = 'DestReg = merge(DestReg, DestReg, dataSize);'

    # Shift instructions