mips,cpu: Get rid of the IsERET StaticInst flag.

This is set by MIPS but doesn't have an accessor in StaticInst, and
isn't used by anything.

Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33738
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/arch/mips/isa/decoder.isa

@@ -719,7 +719,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         LLFlag = 0;
                         Status = status;
                         SRSCtl = srsCtl;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);
 
                     0x1F: deret({{
                         DebugReg debug = Debug;
@@ -732,7 +732,7 @@ decode OPCODE_HI default Unknown::unknown() {
                             // Undefined;
                         }
                         Debug = debug;
-                    }}, IsReturn, IsSerializing, IsERET);
+                    }}, IsReturn, IsSerializing);
                 }
                 format CP0TLB {
                     0x01: tlbr({{

src/cpu/StaticInstFlags.py

@@ -85,7 +85,6 @@ class StaticInstFlags(Enum):
         'IsMemBarrier',     # Is a memory barrier
         'IsWriteBarrier',   # Is a write barrier
         'IsReadBarrier',    # Is a read barrier
-        'IsERET',           # <- Causes the IFU to stall (MIPS ISA)
 
         'IsNonSpeculative', # Should not be executed speculatively
         'IsQuiesce',        # Is a quiesce instruction