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arch-arm: support 64-bit PMCCNTR from AArch32 (#1304)

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For ARMv8 CPUs this register allows reading a 64-bit cycle counter in
from 32-bit execution state.

Change-Id: I7cd9e2711ada5156920440cc3c89e7a74ca54a49
This commit is contained in:
Alexander Richardson
2024-07-02 09:59:44 +02:00
committed by GitHub
parent b28659d4f9
commit d5c0383887
1 changed files with 1 additions and 0 deletions
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src/arch/arm/regs/misc.cc
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@@ -499,6 +499,7 @@ std::unordered_map<MiscRegNum32, MiscRegIndex> miscRegNum32ToIdx{
// MCRR/MRRC regs // MCRR/MRRC regs
{ MiscRegNum32(15, 0, 2), MISCREG_TTBR0 }, { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 },
{ MiscRegNum32(15, 0, 7), MISCREG_PAR }, { MiscRegNum32(15, 0, 7), MISCREG_PAR },
{ MiscRegNum32(15, 0, 9), MISCREG_PMCCNTR }, // ARMv8 AArch32 register
{ MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R }, { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R },
{ MiscRegNum32(15, 0, 14), MISCREG_CNTPCT }, { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT },
{ MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR }, { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },