From d5c0383887483f59c339545e26fe62868d0fb5dd Mon Sep 17 00:00:00 2001 From: Alexander Richardson Date: Tue, 2 Jul 2024 09:59:44 +0200 Subject: [PATCH] arch-arm: support 64-bit PMCCNTR from AArch32 (#1304) For ARMv8 CPUs this register allows reading a 64-bit cycle counter in from 32-bit execution state. Change-Id: I7cd9e2711ada5156920440cc3c89e7a74ca54a49 --- src/arch/arm/regs/misc.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index d6953e91b6..b7779fff76 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -499,6 +499,7 @@ std::unordered_map miscRegNum32ToIdx{ // MCRR/MRRC regs { MiscRegNum32(15, 0, 2), MISCREG_TTBR0 }, { MiscRegNum32(15, 0, 7), MISCREG_PAR }, + { MiscRegNum32(15, 0, 9), MISCREG_PMCCNTR }, // ARMv8 AArch32 register { MiscRegNum32(15, 0, 12), MISCREG_ICC_SGI1R }, { MiscRegNum32(15, 0, 14), MISCREG_CNTPCT }, { MiscRegNum32(15, 0, 15), MISCREG_CPUMERRSR },